Datasheet ADAU1702 (Analog Devices) - 22

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ADAU1702 Data Sheet CONTROL PORTS
The ADAU1702 can operate in one of three control modes: within the ADAU1702 are directly addressable and their sizes exceed the range of single byte addressing. All subsequent bytes I2C control (starting with Byte 3) contain the data, such as control port data, SPI control program data, or parameter data. The number of bytes per word Self-boot (no external controller) depends on the type of data that is being written. The exact formats The ADAU1702 has both a 4-wire SPI control port and a for specific types of writes are shown in Table 20 to Table 29. 2-wire I2C bus control port. Each can be used to set the RAMs The ADAU1702 has several mechanisms for updating signal and registers. When the SELFBOOT pin is low at power-up, the processing parameters in real time without causing pops or part defaults to I2C mode but can be put into SPI control mode clicks. If large blocks of data need to be downloaded, the output by pulling the CLATCH/WP pin low three times. When the of the DSP core can be halted (using the CR bit in the DSP core SELFBOOT pin is set high at power-up, the ADAU1702 loads control register (Address 2076)), new data can be loaded, and its program, parameters, and register settings from an external then the device can be restarted. This is typically done during EEPROM on startup. the booting sequence at startup or when loading a new program The control port is capable of full read/write operation for all into RAM. In cases where only a few parameters need to be addressable memory and registers. Most signal processing changed, they can be loaded without halting the program. To parameters are controlled by writing new values to the parameter avoid unwanted side effects while loading parameters on the fly, the RAM using the control port. Other functions, such as mute and SigmaDSP provides safeload registers. The safeload registers can input/output mode control, are programmed by writing to the be used to buffer a full set of parameters (for example, the five registers. coefficients of a biquad) and then transfer these parameters into the active program within one audio frame. The safeload mode All addresses can be accessed in a single address mode or a uses internal logic to prevent contention between the DSP core burst mode. The first byte (Byte 0) of a control port write and the control port. contains the 7-bit chip address plus the R/W bit. The next two The control port pins are multifunctional, depending on the bytes (Byte 1 and Byte 2) together form the subaddress of the mode in which the part is operating. Table 13 details these memory or register location within the ADAU1702. This multiple functions. subaddress must be two bytes because the memory locations
Table 13. Control Port Pins and SELFBOOT Pin Functions Pin I2C Mode SPI Mode Self-Boot
SCL/CCLK SCL—input CCLK—input SCL—output SDA/COUT SDA—open-collector output COUT—output SDA—open-collector output ADDR1/CDATA/WB ADDR1—input CDATA—input WB—writeback trigger CLATCH/WP Unused input—tie to ground or IOVDD CLATCH—input WP—EEPROM write protect, open-collector output ADDR0 ADDR0—input ADDR0—input Unused input—tie to ground or IOVDD Rev. D | Page 22 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 TO ADDRESS 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 TO ADDRESS 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE