Datasheet ADAU1701 (Analog Devices) - 46
| Manufacturer | Analog Devices |
| Description | SigmaDSP 28/56-Bit Audio Processor with Two ADCs and Four DACs |
| Pages / Page | 52 / 46 — ADAU1701. Data Sheet. Table 63. Serial Output Port Master/Slave Mode … |
| Revision | C |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADAU1701. Data Sheet. Table 63. Serial Output Port Master/Slave Mode Capabilities. 2-Channel Modes. (I2S, Left Justified,
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ADAU1701 Data Sheet
The serial data clocks need to be synchronous with the ADAU1701 input port is set in the serial input control register (Table 50), and master clock input. the configuration of the corresponding output port is control ed The input control register al ows control of clock polarity and with the serial output control register (Table 48). The clocks of data input modes. The valid data formats are I2S, left-justified, the input port function only as slaves, whereas the output port right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In al clocks can be set to function as either masters or slaves. The modes except for the right-justified modes, the serial port accepts INPUT_LRCLK (MP4) and INPUT_BCLK (MP5) pins are an arbitrary number of bits up to a limit of 24. Extra bits do not used to clock the SDATA_INx (MP0 to MP3) signals, and the cause an error, but they are truncated internal y. Proper operation OUTPUT_LRCLK (MP10) and OUTPUT_BCLK (MP11) pins of the right-justified modes requires that there be exactly 64 BCLKs are used to clock the SDATA_OUTx (MP6 to MP9) signals. per audio frame. The TDM data is input on SDATA_IN0. The If an external ADC is connected as a slave to the ADAU1701, LRCLK in TDM mode can be input to the ADAU1701 either as use both the input and output port clocks. The OUTPUT_LRCLK a 50/50 duty cycle clock or as a bit-wide pulse. (MP10) and OUTPUT_BCLK (MP11) pins must be set to master In TDM mode, the ADAU1701 can be a master for 48 kHz and mode and connected external y to the INPUT_LRCLK (MP4) 96 kHz data, but not for 192 kHz data. Table 63 lists the modes and INPUT_BCLK (MP5) pins as well as to the external ADC in which the serial output port can function. clock input pins. The data is output from the external ADC into the SigmaDSP on one of the four SDATA_INx pins (MP0 to MP3).
Table 63. Serial Output Port Master/Slave Mode Capabilities
Connections to an external DAC are handled exclusively with the
2-Channel Modes
output port pins. The OUTPUT_LRCLK and OUTPUT_BCLK
(I2S, Left Justified, f
pins can be set to function as either masters or slaves, and the
S Right Justified) 8-Channel TDM
SDATA_OUTx pins are used to output data from the SigmaDSP 48 kHz Master and slave Master and slave to the external DAC. 96 kHz Master and slave Master and slave 192 kHz Master and slave Slave only Table 65 describes the proper configurations for standard audio data formats. The output control registers allow the user to control clock
Table 64. Multipurpose Pin Serial Data Port Functions
polarities, clock frequencies, clock types, and data format. In all
Multipurpose Pin Function
modes except for the right-justified modes (MSB delayed by 8, MP0 SDATA_IN0/TDM_IN 12, or 16 bits), the serial port accepts an arbitrary number of MP1 SDATA_IN1 bits up to a limit of 24. Extra bits do not cause an error, but are MP2 SDATA_IN2 truncated internal y. Proper operation of the right-justified modes MP3 SDATA_IN3 requires the LSB to align with the edge of the LRCLK. The default MP4 INPUT_LRCLK (slave only) settings of al serial port control registers correspond to 2-channel MP5 INPUT_BCLK (slave only) I2S mode. All register settings apply to both master and slave MP6 SDATA_OUT0/TDM_OUT modes unless otherwise noted. MP7 SDATA_OUT1 The function of each multipurpose pin in serial data port mode MP8 SDATA_OUT2 is shown in Table 64. Pin MP0 to Pin MP5 support digital data MP9 SDATA_OUT3 input to theADAU1701, and Pin MP6 to Pin MP11 handle digital MP10 OUTPUT_LRCLK (master or slave) data output from the DSP. The configuration of the serial data MP11 OUTPUT_BCLK (master or slave)
Table 65. Data Format Configurations LRCLK Format LRCLK Polarity Type BCLK Polarity MSB Position
I2S (Figure 32) Frame begins on falling edge Clock Data changes on falling edge Delayed from LRCLK edge by 1 BCLK Left-Justified (Figure 33) Frame begins on rising edge Clock Data changes on falling edge Aligned with LRCLK edge Right-Justified (Figure 34) Frame begins on rising edge Clock Data changes on falling edge Delayed from LRCLK edge by 8, 12, or 16 BCLKs TDM with Clock (Figure 35) Frame begins on falling edge Clock Data changes on falling edge Delayed from start of word clock by 1 BCLK TDM with Pulse (Figure 36) Frame begins on rising edge Pulse Data changes on falling edge Delayed from start of word clock by 1 BCLK Rev. C | Page 46 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS 2056 (0x0808)—GPIO PIN SETTING REGISTER 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS 2076 (0x081C)—DSP CORE CONTROL REGISTER 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL 2084 (0x0824)—AUXILIARY ADC ENABLE 2086 (0x0826)—OSCILLATOR POWER-DOWN 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE
ADAU1701 Data Sheet
The serial data clocks need to be synchronous with the ADAU1701 input port is set in the serial input control register (Table 50), and master clock input. the configuration of the corresponding output port is control ed The input control register al ows control of clock polarity and with the serial output control register (Table 48). The clocks of data input modes. The valid data formats are I2S, left-justified, the input port function only as slaves, whereas the output port right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In al clocks can be set to function as either masters or slaves. The modes except for the right-justified modes, the serial port accepts INPUT_LRCLK (MP4) and INPUT_BCLK (MP5) pins are an arbitrary number of bits up to a limit of 24. Extra bits do not used to clock the SDATA_INx (MP0 to MP3) signals, and the cause an error, but they are truncated internal y. Proper operation OUTPUT_LRCLK (MP10) and OUTPUT_BCLK (MP11) pins of the right-justified modes requires that there be exactly 64 BCLKs are used to clock the SDATA_OUTx (MP6 to MP9) signals. per audio frame. The TDM data is input on SDATA_IN0. The If an external ADC is connected as a slave to the ADAU1701, LRCLK in TDM mode can be input to the ADAU1701 either as use both the input and output port clocks. The OUTPUT_LRCLK a 50/50 duty cycle clock or as a bit-wide pulse. (MP10) and OUTPUT_BCLK (MP11) pins must be set to master In TDM mode, the ADAU1701 can be a master for 48 kHz and mode and connected external y to the INPUT_LRCLK (MP4) 96 kHz data, but not for 192 kHz data. Table 63 lists the modes and INPUT_BCLK (MP5) pins as well as to the external ADC in which the serial output port can function. clock input pins. The data is output from the external ADC into the SigmaDSP on one of the four SDATA_INx pins (MP0 to MP3).
Table 63. Serial Output Port Master/Slave Mode Capabilities
Connections to an external DAC are handled exclusively with the
2-Channel Modes
output port pins. The OUTPUT_LRCLK and OUTPUT_BCLK
(I2S, Left Justified, f
pins can be set to function as either masters or slaves, and the
S Right Justified) 8-Channel TDM
SDATA_OUTx pins are used to output data from the SigmaDSP 48 kHz Master and slave Master and slave to the external DAC. 96 kHz Master and slave Master and slave 192 kHz Master and slave Slave only Table 65 describes the proper configurations for standard audio data formats. The output control registers allow the user to control clock
Table 64. Multipurpose Pin Serial Data Port Functions
polarities, clock frequencies, clock types, and data format. In all
Multipurpose Pin Function
modes except for the right-justified modes (MSB delayed by 8, MP0 SDATA_IN0/TDM_IN 12, or 16 bits), the serial port accepts an arbitrary number of MP1 SDATA_IN1 bits up to a limit of 24. Extra bits do not cause an error, but are MP2 SDATA_IN2 truncated internal y. Proper operation of the right-justified modes MP3 SDATA_IN3 requires the LSB to align with the edge of the LRCLK. The default MP4 INPUT_LRCLK (slave only) settings of al serial port control registers correspond to 2-channel MP5 INPUT_BCLK (slave only) I2S mode. All register settings apply to both master and slave MP6 SDATA_OUT0/TDM_OUT modes unless otherwise noted. MP7 SDATA_OUT1 The function of each multipurpose pin in serial data port mode MP8 SDATA_OUT2 is shown in Table 64. Pin MP0 to Pin MP5 support digital data MP9 SDATA_OUT3 input to theADAU1701, and Pin MP6 to Pin MP11 handle digital MP10 OUTPUT_LRCLK (master or slave) data output from the DSP. The configuration of the serial data MP11 OUTPUT_BCLK (master or slave)
Table 65. Data Format Configurations LRCLK Format LRCLK Polarity Type BCLK Polarity MSB Position
I2S (Figure 32) Frame begins on falling edge Clock Data changes on falling edge Delayed from LRCLK edge by 1 BCLK Left-Justified (Figure 33) Frame begins on rising edge Clock Data changes on falling edge Aligned with LRCLK edge Right-Justified (Figure 34) Frame begins on rising edge Clock Data changes on falling edge Delayed from LRCLK edge by 8, 12, or 16 BCLKs TDM with Clock (Figure 35) Frame begins on falling edge Clock Data changes on falling edge Delayed from start of word clock by 1 BCLK TDM with Pulse (Figure 36) Frame begins on rising edge Pulse Data changes on falling edge Delayed from start of word clock by 1 BCLK Rev. C | Page 46 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS 2056 (0x0808)—GPIO PIN SETTING REGISTER 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS 2076 (0x081C)—DSP CORE CONTROL REGISTER 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL 2084 (0x0824)—AUXILIARY ADC ENABLE 2086 (0x0826)—OSCILLATOR POWER-DOWN 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE
