Datasheet LTM4646 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Dual 10A or Single 20A μModule Regulator |
| Pages / Page | 36 / 9 — PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin … |
| Revision | A |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) CPWR (F8):. PHASMD (H2):
Model Line for this Datasheet
Text Version of Document
link to page 12 link to page 10 link to page 3 link to page 12 LTM4646
PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) CPWR (F8):
Input Power to the Control IC, and Power RUN pin will turn on the DRVCC, and turn on the INTVCC path to the DRVCC Regulator. This pin is connected to VIN for for operation. See Figure 1 and Applications section. normal 4.5V to 20V operation. For lower voltage inputs below 4.5V, CPWR can be powered with an external 5V
PHASMD (H2):
Connect this pin to SGND, INTVCC, or bias. See Application section. floating this pin to select the phase of CLKOUT and chan- nel 2. See Electrical Characteristics table and Application
COMP1A, COMP2A (G3, E3):
Current Control Threshold. section. These pins are the output of the error amplifier and the switching regulator’s compensation point. The current
PGOOD1, PGOOD2 (G5, E5):
Output Voltage Power Good comparator threshold increases with this control voltage. Indicator. Open-drain logic output that is pulled to ground The voltage ranges from 0V to 2.4V. when the output voltage is not within ±7.5% of the regula- tion point. See Applications section.
COMP1B, COMP2B (G1, E1):
Internal Compensation Network .These pins are to be connected to their respected
INTVCC (F6):
Supply Input for Internal Circuitry (Not COMPA pins. When Utilizing specific external compensa- Including Gate Drivers). This bias is derived from DRVCC tion, then float these pins. internally.
MODE_PLLIN (F3):
Operation Mode Selection or External
EXTVCC (E7):
External Power Input. When EXTVCC exceeds Clock Synchronization Input. When this pin is tied to INTV the switchover voltage (typically 4.6V), an internal switch CC, forced continuous mode operation is selected. Tying this pin connects this pin to DRVCC and shuts down the internal to SGND al ows discontinuous mode operation. When an regulator so that INTVCC and gate drivers draw power external clock is applied at this pin, both channels operate from EXTVCC. The VIN pin still needs to be powered up in forced continuous mode and synchronize to the external but draws minimum current. clock. This pin has an internal 600k pull-down resistor to
TEMP1+,TEMP1– and TEMP2+, TEMP2– (L8, K8 and
SGND. An external clock applied to MODE_PLLIN should
B8, A8):
Onboard temperature diode for monitoring each be within ±30% of this programmed frequency to ensure channel with differential connections for noise immunity. frequency lock.
VIN1 (K4-K5, L4-L5) and VIN2 (A4-A5, B4-B5):
Power
CLKOUT (F4):
Clock output with phase control using the Input Pins. Apply input voltage between these pins and PHASMD pin to enable multiphase operation between GND pins. Recommend placing input decoupling capaci- devices. Its output level swings between INTV tance directly between V CC and SGND. IN pins and GND pins. If clock input is present at the MODE_PLLIN pin, it will
V – OUTS1 (J3):
Differential Output Sense Amplifier (–) Input be synchronized to the input clock, with phase set by the of channel 1. Connect this pin to the negative terminal of PHASMD pin. If no clock is present at MODE_PLLIN, its the output load capacitor of VOUT1. frequency will be set by the FREQ pin. To synchronize other
–
controllers, it can be connected to their MODE_PLLIN pins.
VOUTS2 (D4):
Differential Output Sense Amplifier (–) See the Applications Information section. Input of channel 2. Connect this pin to the negative ter- minal of the output load capacitor of VOUT2.
RUN1, RUN2 (H5, D5):
Run Control Pins. A voltage above 1.3V will turn on each channel in the module. A voltage below
SW1 (H8, J8) and SW2 (C8, D8):
Switching node of each 1.0V on the RUN pin will turn off the related channel. Each channel that is used for testing purposes. Also an R-C RUN pin has a 1.2μA pull-up current, once the RUN pin snubber network can be applied to reduce or eliminate reaches 1.2V an additional 4.5μA pull-up current is added switch node ringing, or otherwise leave floating. See the to this pin. A 100k resistor to ground is internal, and can be Applications Information section. used with a pull-up resistor to VIN to turn on the module using
VRNG (D2):
Current Limit Adjustment Range. Tying this the external and internal resistor to program under voltage pin to INTVCC sets full 10A current, or tying to SGND will lockout. Otherwise, an external enable signal or source can lower the current limit to 5A. Default to INTVCC. drive these pins directly below the 6V max. Enabling either Rev. A For more information www.analog.com 9 Document Outline Operation Applications Information Package Description Package Photo Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts
PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) CPWR (F8):
Input Power to the Control IC, and Power RUN pin will turn on the DRVCC, and turn on the INTVCC path to the DRVCC Regulator. This pin is connected to VIN for for operation. See Figure 1 and Applications section. normal 4.5V to 20V operation. For lower voltage inputs below 4.5V, CPWR can be powered with an external 5V
PHASMD (H2):
Connect this pin to SGND, INTVCC, or bias. See Application section. floating this pin to select the phase of CLKOUT and chan- nel 2. See Electrical Characteristics table and Application
COMP1A, COMP2A (G3, E3):
Current Control Threshold. section. These pins are the output of the error amplifier and the switching regulator’s compensation point. The current
PGOOD1, PGOOD2 (G5, E5):
Output Voltage Power Good comparator threshold increases with this control voltage. Indicator. Open-drain logic output that is pulled to ground The voltage ranges from 0V to 2.4V. when the output voltage is not within ±7.5% of the regula- tion point. See Applications section.
COMP1B, COMP2B (G1, E1):
Internal Compensation Network .These pins are to be connected to their respected
INTVCC (F6):
Supply Input for Internal Circuitry (Not COMPA pins. When Utilizing specific external compensa- Including Gate Drivers). This bias is derived from DRVCC tion, then float these pins. internally.
MODE_PLLIN (F3):
Operation Mode Selection or External
EXTVCC (E7):
External Power Input. When EXTVCC exceeds Clock Synchronization Input. When this pin is tied to INTV the switchover voltage (typically 4.6V), an internal switch CC, forced continuous mode operation is selected. Tying this pin connects this pin to DRVCC and shuts down the internal to SGND al ows discontinuous mode operation. When an regulator so that INTVCC and gate drivers draw power external clock is applied at this pin, both channels operate from EXTVCC. The VIN pin still needs to be powered up in forced continuous mode and synchronize to the external but draws minimum current. clock. This pin has an internal 600k pull-down resistor to
TEMP1+,TEMP1– and TEMP2+, TEMP2– (L8, K8 and
SGND. An external clock applied to MODE_PLLIN should
B8, A8):
Onboard temperature diode for monitoring each be within ±30% of this programmed frequency to ensure channel with differential connections for noise immunity. frequency lock.
VIN1 (K4-K5, L4-L5) and VIN2 (A4-A5, B4-B5):
Power
CLKOUT (F4):
Clock output with phase control using the Input Pins. Apply input voltage between these pins and PHASMD pin to enable multiphase operation between GND pins. Recommend placing input decoupling capaci- devices. Its output level swings between INTV tance directly between V CC and SGND. IN pins and GND pins. If clock input is present at the MODE_PLLIN pin, it will
V – OUTS1 (J3):
Differential Output Sense Amplifier (–) Input be synchronized to the input clock, with phase set by the of channel 1. Connect this pin to the negative terminal of PHASMD pin. If no clock is present at MODE_PLLIN, its the output load capacitor of VOUT1. frequency will be set by the FREQ pin. To synchronize other
–
controllers, it can be connected to their MODE_PLLIN pins.
VOUTS2 (D4):
Differential Output Sense Amplifier (–) See the Applications Information section. Input of channel 2. Connect this pin to the negative ter- minal of the output load capacitor of VOUT2.
RUN1, RUN2 (H5, D5):
Run Control Pins. A voltage above 1.3V will turn on each channel in the module. A voltage below
SW1 (H8, J8) and SW2 (C8, D8):
Switching node of each 1.0V on the RUN pin will turn off the related channel. Each channel that is used for testing purposes. Also an R-C RUN pin has a 1.2μA pull-up current, once the RUN pin snubber network can be applied to reduce or eliminate reaches 1.2V an additional 4.5μA pull-up current is added switch node ringing, or otherwise leave floating. See the to this pin. A 100k resistor to ground is internal, and can be Applications Information section. used with a pull-up resistor to VIN to turn on the module using
VRNG (D2):
Current Limit Adjustment Range. Tying this the external and internal resistor to program under voltage pin to INTVCC sets full 10A current, or tying to SGND will lockout. Otherwise, an external enable signal or source can lower the current limit to 5A. Default to INTVCC. drive these pins directly below the 6V max. Enabling either Rev. A For more information www.analog.com 9 Document Outline Operation Applications Information Package Description Package Photo Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts
