Datasheet ADSP-21477, ADSP-21478, ADSP-21479 (Analog Devices) - 4

link to page 1 link to page 5 link to page 5 link to page 5
ADSP-21477/ ADSP-21478/ ADSP-21479
The block diagram of the ADSP-2147x on Page 1 also shows the elements. When using the DAGs to transfer data in SIMD peripheral clock domain (also known as the I/O processor), mode, two data values are transferred with each memory or reg- which contains the following features: ister file access. • IOD0 (periphera l DMA) and IOD1 (external port DMA) SIMD mode is supported from external SDRAM but is not sup- buses for 32-bit data transfers ported in the AMI. • Peripheral and external port buses for core connection
Independent, Parallel Computation Units
• External port with an asynchronous memory interface Within each processing element is a set of computational units. (AMI) and SDRAM controller The computational units consist of an arithmetic/logic unit • 4 units for pulse width modulation (PWM) control (ALU), multiplier, and shifter. These units perform all opera- • 1 memory-to-memory (MTM) unit for internal-to-internal tions in a single cycle. The three units within each processing memory transfers element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel • Digital applications interface that includes four precision ALU and multiplier operations. In SIMD mode, the parallel clock generators (PCG), an input data port (IDP/PDAP) ALU and multiplier operations occur in both processing ele- for serial and parallel interconnect, an S/PDIF ments. These computation units support IEEE 32-bit single- receiver/transmitter, four asynchronous sample rate con- precision floating-point, 40-bit extended precision floating- verters, eight serial ports, a shift register, and a flexible point, and 32-bit fixed-point data formats. signal routing unit (DAI SRU).
Timer
• Digital peripheral interface that includes two timers, a 2- wire interface, one UART, two serial peripheral interfaces The processor contains a core timer that can generate periodic (SPI), two precision clock generators (PCG), three pulse software interrupts. The core timer can be configured to use width modulation (PWM) units, and a flexible signal rout- FLAG3 as a timer expired signal. ing unit (DPI SRU).
Data Register File
As shown in the SHARC core block diagram on Page 5, the pro- cessors use two computational units to deliver a significant Each processing element contains a general-purpose data regis- performance increase over the previous SHARC processors on a ter file. The register files transfer data between the computation range of DSP algorithms. With its SIMD computational hard- units and the data buses, and store intermediate results. These ware, the processors can perform 1.8 GFLOPS running at 10-port, 32-register (16 primary, 16 secondary) register files, 300 MHz. combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and
FAMILY CORE ARCHITECTURE
internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. The processors are code compatible at the assembly level with the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,
Context Switch
ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2147x share archi- Many of the processor’s registers have secondary registers that tectural features with the ADSP-2126x, ADSP-2136x, ADSP- can be activated during interrupt servicing for a fast context 2137x, ADSP-2146x, and ADSP-2116x SIMD SHARC proces- switch. The data registers in the register file, the DAG registers, sors, as shown in Figure 2 and detailed in the following sections. and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary
SIMD Computational Engine
registers are activated by control bits in a mode control register. The processors contain two computational processing elements
Universal Registers
that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY Universal registers can be used for general-purpose tasks. The and each contains an ALU, multiplier, shifter, and register file. USTAT (4) registers allow easy bit manipulations (Set, Clear, PEX is always active, and PEY may be enabled by setting the Toggle, Test, XOR) for all peripheral control and status PEYEN mode bit in the MODE1 register. SIMD mode allows registers. the processor to execute the same instruction in both processing The data bus exchange register (PX) permits data to be passed elements, but each processing element operates on different between the 64-bit PM data bus and the 64-bit DM data bus, or data. This architecture is efficient at executing math intensive between the 40-bit register file and the PM/DM data bus. These DSP algorithms. registers contain hardware to handle the data width difference. SIMD mode also affects the way data is transferred between
Single-Cycle Fetch of Instruction and Four Operands
memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the The processors feature an enhanced Harvard architecture in processing elements. Therefore, entering SIMD mode also dou- which the data memory (DM) bus transfers data and the pro- bles the bandwidth between memory and the processing gram memory (PM) bus transfers both instructions and data (see Figure 2). With its separate program and data memory Rev. D | Page 4 of 76 | April 2017 Document Outline SHARC Processor Summary Revision History Product Application Restriction General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth ROM Based Security Digital Transmission Content Protection Family Peripheral Architecture External Memory External Port SIMD Access to External Memory VISA and ISA Access to External Memory SDRAM Controller Asynchronous Memory Controller External Port Throughput MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Pulse-Width Modulation Timers 2-Wire Interface Port (TWI) Shift Register I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer (WDT) Real-Time Clock System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Maximum Power Dissipation Package Information ESD Sensitivity Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Shift Register Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-LFCSP_VQ Lead Assignment 100-LQFP_EP Lead Assignment 196-BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide