Datasheet XF (IDT)

ManufacturerIDT
Description150fs Small Package Quartz-based PLL Oscillator
Pages / Page17 / 1 — XF Family of Low Phase Noise. Quartz-based PLL Oscillators. Datasheet. …
Revision20190403
File Format / SizePDF / 385 Kb
Document LanguageEnglish

XF Family of Low Phase Noise. Quartz-based PLL Oscillators. Datasheet. Description. Features. Typical Applications. Pin Assignments

Datasheet XF IDT, Revision: 20190403

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XF Family of Low Phase Noise XF Quartz-based PLL Oscillators Datasheet Description Features
The XF devices are ultra-low phase noise quartz-based PLL ▪ Output types: LVDS, LVPECL, CML oscillators supporting a large range of frequencies and output • Frequency range: 15MHz to 2100MHz interface types. These devices are designed to operate at three ▪ Output type: HCSL different power supplies with several pinout configurations, as well as two operational temperature ranges. • Frequency range: 15MHz to 725MHz ▪ Supply voltage options: 1.8V, 2.5V, or 3.3V The XF devices can be programmed to generate an output ▪ frequency from 15MHz to 2100MHz with a resolution as low as Phase jitter (12kHz to 20MHz): 120fs typical 1Hz accuracy. The configuration capability of this family of devices ▪ Package: 2.5 × 2.0 mm, 0.4mm pitch DFN allows for fast delivery times for both sample and large production ▪ Operating temperatures and frequency stability: orders. • -40°C to +85°C, ±25ppm Parts are for one time programming (OTP) at the factory for a • -40°C to +105°C, ±50ppm fixed frequency application, or can be field programmable using I2C, based on system needs (see notes under Pin Descriptions).
Typical Applications Pin Assignments
▪ FOM Gear Box ▪ Data centers NC 1 12 Ground Core ▪ 10G / 40G / 100G / 400G Ethernet NC 2 11 VDD Core Voltage Control 3 10 Ground Output SDA 4 9 Output 0b OE 5 8 Output 0 SCL 6 7 VDD Output
Table 1. Pin Descriptions Pin Number Pin Name Description
1 NC No connect. 2 NC No connect. 3 Voltage Control 2 Voltage control for VCXO option. 4 SDA 1 Serial data. 5 OE Output enable. 6 SCL 1 Serial clock. 7 VDD Output Supply voltage. 8 Output 0 Output 0. 9 Output 0b Complementary output 0. 10 Ground Output Connect to ground. 11 VDD Core Supply voltage. 12 Ground Core Connect to ground. 13 EPAD (dotted area shown in Pin Assignments diagram) Connect to ground (required for heat dissipation). 1 Pins 4 and 6 are no connect for I2C applications. 2 Pin 3 is no connect for analog VCXO applications. See Ordering Information for more details. ©2019 Integrated Device Technology, Inc. 1 April 3, 2019 Document Outline Description Pin Assignments Features Typical Applications Table 1. Pin Descriptions Absolute Maximum Ratings Table 2. Absolute Maximum Ratings ESD Compliance Table 3. ESD Compliance Mechanical Testing Table 4. Mechanical Testing * Solder Reflow Profile DC Electrical Characteristics Table 5. 3.3V IDD DC Electrical Characteristics Table 6. 2.5V IDD DC Electrical Characteristics Table 7. 1.8V IDD DC Electrical Characteristics Table 8. LVCMOS DC Electrical Characteristics Table 9. LVDS DC Electrical Characteristics Table 10. LVPECL DC Electrical Characteristics Table 11. HCSL DC Electrical Characteristics Table 12. CML DC Electrical Characteristics Table 13. DC Electrical Characteristics – Leakage Current AC Electrical Characteristics Table 14. 3.3V AC Electrical Characteristics Table 15. 2.5V AC Electrical Characteristics Table 16. 1.8V AC Electrical Characteristics Table 17. Phase Jitter Characteristics Output Waveforms Figure 1. LVDS Output Waveforms Figure 2. LVPECL Output Waveforms Figure 3. HCSL Output Waveforms Figure 4. CML Output Waveforms Termination for 3.3V LVPECL Outputs Figure 5. 3.3V LVPECL Output Termination Figure 6. 3.3V LVPECL Output Termination Termination for 2.5V LVPECL Outputs Figure 7. 2.5V LVPECL Driver Termination Example Figure 8. 2.5V LVPECL Driver Termination Example Figure 9. 2.5V LVPECL Driver Termination Example LVDS Driver Termination Figure 10. Standard LVDS Termination Figure 11. Optional LVDS Termination Recommended Termination for HCSL Outputs Figure 12. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 13. Recommended Termination (where a point-to-point connection can be used) CML Termination Figure 14. CML Termination Example Package Outline Drawings Marking Diagram Ordering Information Revision History
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