Datasheet XP (IDT)

Description150fs Quartz-based PLL Oscillator
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XP Family of Ultra-low Phase Noise. Quartz-based PLL Oscillators. Datasheet. Description. Features

Datasheet XP IDT, Revision: 20190401

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XP Family of Ultra-low Phase Noise XP Quartz-based PLL Oscillators Datasheet Description Features
The XP devices are ultra-low phase noise quartz-based PLL ▪ Output types: LVDS, LVPECL, CML oscillators supporting a large range of frequencies and output • Frequency range: 15MHz to 2100MHz interface types. These devices are designed to operate at three ▪ Output type: HCSL different power supplies and are available in three package sizes with several pinout configurations, as well as three operational • Frequency range: 15MHz to 725MHz temperature ranges. ▪ Supply voltage options: 1.8V, 2.5V, or 3.3V ▪ The XP devices can be programmed to generate an output Phase jitter (12kHz to 20MHz): 120fs typical frequency from 15MHz to 2100MHz with a resolution as low as ▪ Package options: 1Hz accuracy. The configuration capability of this family of devices • 7.0 × 5.0 × 1.7 mm allows for fast delivery times for both sample and large production • 5.0 × 3.2 × 1.17 mm orders. • 3.2 × 2.5 × 1.07 mm Parts are for one time programming (OTP) at the factory for a ▪ Operating temperatures and frequency stability: fixed frequency application, or can be field programmable using • -40°C to +85°C, ±25ppm I2C, based on system needs (see note 1 under Pin Descriptions). • -40°C to +105°C, ±50ppm
Pin Assignments Figure 1. 7.0 × 5.0 mm, 5.0 × 3.2 mm, and 3.2 × 2.5 mm Packages
SDA 7 OE 1 6 VDD NC 2 5 OUT0b GND 3 4 OUT0 8 SCL
Table 1. Pin Descriptions Pin # Pin Name Description
1 OE Output Enable (0 = output disabled, pulled high internally) 2 NC No connect 3 GND Connect to ground 4 OUT0 Output 5 OUT0b Complementary output 6 VDD Supply voltage 7 SDA 1 Serial data 8 SCL 1 Serial clock 1 Pins 7 and 8 are no connect for non-I2C applications. See Ordering Information for more details. ©2019 Integrated Device Technology, Inc. 1 April 1, 2019 Document Outline Description Features Pin Assignments Figure 1. 7.0 × 5.0 mm, 5.0 × 3.2 mm, and 3.2 × 2.5 mm Packages Table 1. Pin Descriptions Absolute Maximum Ratings Table 2. Absolute Maximum Ratings ESD Compliance Table 3. ESD Compliance Mechanical Testing Table 4. Mechanical Testing * Solder Reflow Profile DC Electrical Characteristics Table 5. 3.3V IDD DC Electrical Characteristics Table 6. 2.5V IDD DC Electrical Characteristics Table 7. 1.8V IDD DC Electrical Characteristics Table 8. LVCMOS DC Electrical Characteristics Table 9. LVDS DC Electrical Characteristics Table 10. LVPECL DC Electrical Characteristics Table 11. HCSL DC Electrical Characteristics Table 12. CML DC Electrical Characteristics Table 13. DC Electrical Characteristics – Leakage Current AC Electrical Characteristics Table 14. 3.3V AC Electrical Characteristics Table 15. 2.5V AC Electrical Characteristics Table 16. 1.8V AC Electrical Characteristics Table 17. Phase Jitter Characteristics Output Waveforms Figure 2. LVDS Output Waveforms Figure 3. LVPECL Output Waveforms Figure 4. HCSL Output Waveforms Figure 5. CML Output Waveforms Termination for 3.3V LVPECL Outputs Figure 6. 3.3V LVPECL Output Termination Figure 7. 3.3V LVPECL Output Termination Termination for 2.5V LVPECL Outputs Figure 8. 2.5V LVPECL Driver Termination Example Figure 9. 2.5V LVPECL Driver Termination Example Figure 10. 2.5V LVPECL Driver Termination Example LVDS Driver Termination Figure 11. Standard LVDS Termination Figure 12. Optional LVDS Termination Recommended Termination for HCSL Outputs Figure 13. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 14. Recommended Termination (where a point-to-point connection can be used) CML Termination Figure 15. CML Termination Example Package Outline Drawings Marking Diagrams Figure 16. Marking Configuration for the 7.0 × 5.0 mm and 5.0 × 3.2 mm Packages Figure 17. Marking Configuration for the 3.2 × 2.5 mm Package Ordering Information Revision History
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