Datasheet ADuM3220/ADuM3221 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Isolated 4 A Dual-Channel Gate Driver |
| Pages / Page | 16 / 4 — ADuM3220/ADuM3221. Data Sheet. ELECTRICAL CHARACTERISTICS—3.3 V … |
| Revision | C |
| File Format / Size | PDF / 622 Kb |
| Document Language | English |
ADuM3220/ADuM3221. Data Sheet. ELECTRICAL CHARACTERISTICS—3.3 V OPERATION. Table 2. Parameter. Symbol. Min. Typ. Max. Unit
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ADuM3220/ADuM3221 Data Sheet ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 10 V. Switching specifications are tested with CMOS signal levels.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS Input Supply Current, Two Channels, Quiescent IDDI(Q) 0.7 1.0 mA Output Supply Current, Two Channels, IDDO(Q) 4.7 10 mA Quiescent Total Supply Current, Two Channels1 DC to 1 MHz VDD1 Supply Current IDD1(Q) 0.8 1.0 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2(Q) 11 17 mA DC to 1 MHz logic signal frequency Input Currents IIA, IIB −10 +0.01 +10 µA 0 V ≤ VIA, VIB ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH, VOBH VDD2 − 0.1 VDD2 V IOx = −20 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.15 V IOx = +20 mA, VIx = VIxL Undervoltage Lockout, VDD2 Supply ADuM3220A/ADuM3221A Positive-Going Threshold VDD2UV+ 4.1 4.4 V Negative-Going Threshold VDD2UV− 3.2 3.7 V Hysteresis VDD2UVH 0.4 V ADuM3220B/ADuM3221B Positive-Going Threshold VDD2UV+ 7.0 7.5 V Negative-Going Threshold VDD2UV− 6.0 6.5 V Hysteresis VDD2UVH 0.5 V Output Short-Circuit Pulsed Current2 IOA(SC), IOB(SC) 2.0 4.0 A VDD2 = 10 V Output Pulsed Source Resistance ROA, ROB 0.3 1.3 3.0 Ω VDD2 = 10 V Output Pulsed Sink Resistance ROA, ROB 0.3 0.9 3.0 Ω VDD2 = 10 V SWITCHING SPECIFICATIONS Pulse Width3 PW 50 ns CL = 2 nF, VDD2 = 10 V Data Rate4 1 MHz CL = 2 nF, VDD2 = 10 V Propagation Delay5 tDLH, tDHL 36 48 62 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 tDLH, tDHL 37 53 72 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 20 Propagation Delay Skew6 tPSK 12 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 Channel-to-Channel Matching7 tPSKCD 1 5 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 tPSKCD 1 7 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 20 Output Rise/Fall Time (10% to 90%) tR/tF 14 20 25 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 tR/tF 14 22 28 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 20 Dynamic Input Supply Current per Channel IDDI(D) 0.025 mA/Mbps VDD2 = 10 V Dynamic Output Supply Current per Channel IDDO(D) 1.5 mA/Mbps VDD2 = 10 V Refresh Rate fr 1.1 Mbps 1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 9 and Figure 10 for total VDD1 and VDD2 supply currents as a function of frequency. 2 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section. 3 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 5 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay parameters. 6 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters. 7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Rev. C | Page 4 of 16 Document Outline Features Applications General Description Functional Block Diagrams Table of Contents Revision History Specifications Electrical Characteristics—5 V Operation Electrical Characteristics—3.3 V Operation Package Characteristics Regulatory Information Insulation and Safety-Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Recommended Operating Conditions Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Applications Information PC Board Layout Propagation Delay-Related Parameters Thermal Limitations and Switch Load Characteristics Output Load Characteristics DC Correctness and Magnetic Field Immunity Power Consumption Insulation Lifetime Outline Dimensions Ordering Guide Automotive Products
ADuM3220/ADuM3221 Data Sheet ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 10 V. Switching specifications are tested with CMOS signal levels.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS Input Supply Current, Two Channels, Quiescent IDDI(Q) 0.7 1.0 mA Output Supply Current, Two Channels, IDDO(Q) 4.7 10 mA Quiescent Total Supply Current, Two Channels1 DC to 1 MHz VDD1 Supply Current IDD1(Q) 0.8 1.0 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2(Q) 11 17 mA DC to 1 MHz logic signal frequency Input Currents IIA, IIB −10 +0.01 +10 µA 0 V ≤ VIA, VIB ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH, VOBH VDD2 − 0.1 VDD2 V IOx = −20 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.15 V IOx = +20 mA, VIx = VIxL Undervoltage Lockout, VDD2 Supply ADuM3220A/ADuM3221A Positive-Going Threshold VDD2UV+ 4.1 4.4 V Negative-Going Threshold VDD2UV− 3.2 3.7 V Hysteresis VDD2UVH 0.4 V ADuM3220B/ADuM3221B Positive-Going Threshold VDD2UV+ 7.0 7.5 V Negative-Going Threshold VDD2UV− 6.0 6.5 V Hysteresis VDD2UVH 0.5 V Output Short-Circuit Pulsed Current2 IOA(SC), IOB(SC) 2.0 4.0 A VDD2 = 10 V Output Pulsed Source Resistance ROA, ROB 0.3 1.3 3.0 Ω VDD2 = 10 V Output Pulsed Sink Resistance ROA, ROB 0.3 0.9 3.0 Ω VDD2 = 10 V SWITCHING SPECIFICATIONS Pulse Width3 PW 50 ns CL = 2 nF, VDD2 = 10 V Data Rate4 1 MHz CL = 2 nF, VDD2 = 10 V Propagation Delay5 tDLH, tDHL 36 48 62 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 tDLH, tDHL 37 53 72 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 20 Propagation Delay Skew6 tPSK 12 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 Channel-to-Channel Matching7 tPSKCD 1 5 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 tPSKCD 1 7 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 20 Output Rise/Fall Time (10% to 90%) tR/tF 14 20 25 ns CL = 2 nF, VDD2 = 10 V; see Figure 20 tR/tF 14 22 28 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 20 Dynamic Input Supply Current per Channel IDDI(D) 0.025 mA/Mbps VDD2 = 10 V Dynamic Output Supply Current per Channel IDDO(D) 1.5 mA/Mbps VDD2 = 10 V Refresh Rate fr 1.1 Mbps 1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 9 and Figure 10 for total VDD1 and VDD2 supply currents as a function of frequency. 2 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section. 3 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 5 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay parameters. 6 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters. 7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Rev. C | Page 4 of 16 Document Outline Features Applications General Description Functional Block Diagrams Table of Contents Revision History Specifications Electrical Characteristics—5 V Operation Electrical Characteristics—3.3 V Operation Package Characteristics Regulatory Information Insulation and Safety-Related Specifications DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics Recommended Operating Conditions Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Applications Information PC Board Layout Propagation Delay-Related Parameters Thermal Limitations and Switch Load Characteristics Output Load Characteristics DC Correctness and Magnetic Field Immunity Power Consumption Insulation Lifetime Outline Dimensions Ordering Guide Automotive Products
