Datasheet ACS724KMA (Allegro) - 4
| Manufacturer | Allegro |
| Description | High-Accuracy, Hall-Effect-Based Current Sensor IC with Common-Mode Field Rejection in Reinforced-Isolation SOICW-16 Package |
| Pages / Page | 22 / 4 — High-Accuracy, Hall-Effect-Based Current Sensor IC. ACS724KMA |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
High-Accuracy, Hall-Effect-Based Current Sensor IC. ACS724KMA
Model Line for this Datasheet
Text Version of Document
High-Accuracy, Hall-Effect-Based Current Sensor IC ACS724KMA with Common-Mode Field Rejection in High-Isolation SOIC16 Package
VCC VCC Master Current To All Subcircuits Supply Programming Control POR Hall Current Temperature EEPROM and CBYPASS Drive Sensor Control Logic 0.1 µF Offset IP+ Control IP+ Sensitivity IP+ Control IP+ ffset n
+
O latio
+ –
VIOUT cel RF(int)
–
ynamic an IP– D C IP– IP– IP– GND C FILTER F
Functional Block Diagram
IP+ 1 16 NC
Terminal List Table
IP+ 2 15 GND
Number Name Description
IP+ 3 14 NC 1, 2, 3, 4 IP+ Terminals for current being sensed; fused internally IP+ 4 13 FILTER 5, 6, 7, 8 IP- Terminals for current being sensed; fused internally IP- 5 12 VIOUT IP- 6 11 NC 9, 16 NC No internal connection; recommended to be left unconnected in order to maintain high creepage IP- 7 10 VCC 10 VCC Device power supply terminal IP- 8 9 NC 11, 14 NC No internal connection; recommened to connect to GND for the best ESD performance 12 VIOUT Analog output signal
Pinout Diagram
13 FILTER Terminal for external capacitor that sets bandwidth 15 GND Signal ground terminal 4 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com
VCC VCC Master Current To All Subcircuits Supply Programming Control POR Hall Current Temperature EEPROM and CBYPASS Drive Sensor Control Logic 0.1 µF Offset IP+ Control IP+ Sensitivity IP+ Control IP+ ffset n
+
O latio
+ –
VIOUT cel RF(int)
–
ynamic an IP– D C IP– IP– IP– GND C FILTER F
Functional Block Diagram
IP+ 1 16 NC
Terminal List Table
IP+ 2 15 GND
Number Name Description
IP+ 3 14 NC 1, 2, 3, 4 IP+ Terminals for current being sensed; fused internally IP+ 4 13 FILTER 5, 6, 7, 8 IP- Terminals for current being sensed; fused internally IP- 5 12 VIOUT IP- 6 11 NC 9, 16 NC No internal connection; recommended to be left unconnected in order to maintain high creepage IP- 7 10 VCC 10 VCC Device power supply terminal IP- 8 9 NC 11, 14 NC No internal connection; recommened to connect to GND for the best ESD performance 12 VIOUT Analog output signal
Pinout Diagram
13 FILTER Terminal for external capacitor that sets bandwidth 15 GND Signal ground terminal 4 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com
