Datasheet AD7768-1 (Analog Devices) - 48

AD7768-1 Data Sheet SPI CONTROL MODE
When using the SYNC_OUT function with an IOVDD voltage of
MCLK Source and MCLK Division
1.8 V, it is recommended to set the SYNC_OUT_POS_EDGE bit MCLK division bits control the divided ratio between the MCLK to a one (Register 0x1D, Bit 6). applied at the input to the AD7768-1 and the clock used by the
Offset Calibration
ADC modulator. Select the division ratio best for configuration In SPI control mode, the AD7768-1 offers the ability to calibrate of the clocks. offset and gain. The user can alter the gain and offset of the The fol owing options are available as the MCLK input source AD7768-1 and its subsystem. These options are available in in SPI mode: SPI control mode only. • LVDS The offset correction registers provide 24-bit, signed, twos • External crystal complement registers for channel offset adjustment. If the channel • CMOS input MCLK gain setting is at the ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by −4/3 LSBs. Pulling CLOCK_SEL low configures the AD7768-1 for a CMOS For example, changing the offset register from 0 to 100 changes clock. Pulling CLOCK_SEL high enables the use of an external the digital output by −133 LSBs. As offset calibration occurs before crystal. gain calibration, the LSB ratio of −4/3 changes linearly with gain Pulling CLOCK_SEL high and setting Bits[7:6] of Register 0x15 adjustment via the gain correction registers. enables the application of the LVDS clock to the MCLK pin. Further register information and calibration instructions are LVDS clocking is exclusive to SPI mode and requires the available within the offset registers. register selection for operation.
Gain Calibration Power-Down Mode
In SPI control mode, the user can alter the gain and offset of the Power-down mode has the lowest possible current consumption. AD7768-1 and its subsystem. These options are available in SPI All blocks on the ADC are turned off. A specific code is required control mode only. to wake the ADC up. All register contents are lost when entering power-down mode. Disconnect all inputs to the ADC when The ADC has an associated gain coefficient that is stored for entering power-down mode. See the power and clock control each ADC after factory programming. Nominally, this gain is register (POWER_CLOCK), Register 0x15, for further details. approximately the 0x555555 value (for an ADC channel). The user can overwrite the gain register setting. However, after a
Standby Mode
reset or power cycle, the gain register values revert to the hard Analog clocking and power functions are powered down. The coded, programmed factory setting. digital LDO and register settings are retained when in standby  ×  mode. This mode is best used in scenarios where the ADC is 3 I V N 21 Gain 4,194,300 Data = ×2 −(Offset) × ×   42 not in use, briefly, and the user wants to save power.  RE V F  4 2
SPI Synchronization
Further register information and calibration instructions are available within the gain registers. The AD7768-1 can be synchronized over the SPI. The final SCLK rising edge of the command is the instance of synchronization.
Reset over SPI Control Interface
This command initiates the SYNC_OUT pin to pulse active The user can issue a reset command to the AD7768-1 by writing to low and then back active high again. SYNC_OUT is a signal the SPI_RESET bits in the SYNC_RESET register. Two successive synchronized internal y to the MCLK of the ADC. By connecting writes to these bits are required to initiate the device reset. the output of SYNC_OUT to the SYNC_IN input, the user can
Resume from Shutdown
synchronize that individual ADC. Routing SYNC_OUT to other Shutdown mode features the lowest possible current consumption AD7768-1 devices also ensures the devices are synchronized, as with all blocks on the device turned off, including the standard long as the devices share a common MCLK source. SPI interface. Therefore, to wake the ADC up from this mode, It is recommended to perform synchronization functions directly either a hardware reset on the RESET pin, or a specific code on after the DRDY pulse. If the AD7768-1 SYNC_IN pulse occurs the SPI SDI input, is required. The specific sequence required too close to the upcoming DRDY pulse edge, the upcoming on SDI consists of a 1 followed by 63 zeros, clocked in by SCLK DRDY pulse may stil be output because the SYNC_IN pulse while CS is low, which allows the system to wake up the AD7768-1 has not yet propagated through the device. from shutdown without using the RESET pin. This reset function is useful in isolated applications where the number of pins brought across the isolation barrier must be minimized. Rev. A | Page 48 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE