Datasheet AD7768-1 (Analog Devices) - 61

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Data Sheet AD7768-1 RECOMMENDED INTERFACE
3. Issue a synchronization pulse to apply the changes to the The AD7768-1 interface is flexible to allow the many modes of digital domain and to reset the digital filter. Issue the pulse operation and for data output formats to work across different immediately after DRDY goes high. DSPs and microcontroller units (MCUs). To achieve maximum
Recommended Interface for Reading Data
performance, the recommended interface configuration for The recommended interface for reading data is as follows: reading conversion results is shown in Figure 98. This recommended 1. Synchronize the host control er with the DRDY or RDY implementation uses a synchronous SCLK to MCLK relationship. pulse. See Figure 6 for details on the RDY behavior before Configure the interface as fol ows to achieve the recommended data is clocked out. operation: 2. Generate SCLK based on the DRDY or RDY timing. SCLK 1. Tie the CS signal low during the conversion readback. is high when the DRDY signal goes high and transitions on 2. Enter continuous readback mode to avoid needing to provide the MCLK fal ing edges (see Figure 98) to ensure that the the address bits for the ADC_DATA register. Continuous LSB can be read correctly as the DOUT/RDY output is readback mode is the default readback mode in PIN mode. reset on the DRDY rising edge. However, SCLK rising 3. 32 bits of data are clocked out, consisting of the 24-bit occurs before this transition. conversion result plus eight bits that can be selected to be 3. The MSB is clocked out on the next fal ing edge of SCLK. either the status or CRC bits. In PIN mode, this is always 4. In PIN control mode, the LSB of the conversion output is the conversion result plus the eight status bits. the last bit of the status output. In PIN control mode, this 4. Provide an SCLK that is a divided down version of MCLK. bit is always 1 and, therefore, does not need to be read. For example, SCLK = MCLK/2 in a case where decimate by
Resynchronization of the Recommended Interface
32 is selected. 5. Because the ful ODR period is for clocking data, the RDY Clocking 32 bits ensures that the data readback operation fills the entire DRDY period when SCLK = MCLK/2. SCLK signal no longer flags after each LSB outputs. This signal only flags if the AD7768-1 is in continuous readback mode, or if the runs continuously. The readback spans the full DRDY period, AD7768-1 does not count 32 SCLKs within 1 × t thus spreading the dynamic current needed on IOVDD MCLK before DRDY, as is shown in Figure 98. across the full ODR period. 6. The DRDY signal can synchronize the data being read into The RDY function is only available in continuous readback the host controller. mode. In normal readback, where the ADC_DATA register must be addressed each time, the DOUT line is reset 1 × t Figure 98 shows how the recommended interface operates. The MCLK before DRDY, as per t data read back spans the entire length of the DRDY period and 10 in the Timing Specifications section. If DRDY is used, the device operates as normal, and conversion readback the LSB remains until DRDY goes high for the next conversion. is timed from the DRDY pulse. In the case where RDY detects
Initializing the Recommended Interface
the beginning of each sample, and where the data readback To configure the recommended interface, take the fol owing steps: loses synchronization, the SCLK timing can be recovered by 1. one of the following two methods: Configure the device settings, such as power mode, decimation ratio, filter type, and so on. • Using CS to reset the interface and to observe the RDY 2. transition. Enter continuous readback mode. • Stopping SCLK toggling until the RDY transition is detected one more time.
MCLK DRDY SCLK DRIVE EDGE SAMPLE EDGE SDI DOUT/RDY LSB + 1 LSB MSB MSB – 1 SCLK = MCLK/2 t t t 4 3 MCLK_DRDY
092
LSB REMAINS UNTIL DRDY GOES HIGH
16481- Figure 98. Recommended Interface for Reading Conversions, SPI Control, Continuous Readback Mode Rev. A | Page 61 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE