Datasheet AD7980-EP (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP |
| Pages / Page | 12 / 5 — Enhanced Product. AD7980-EP. TIMING SPECIFICATIONS. Table 4. Parameter. … |
| Revision | A |
| File Format / Size | PDF / 340 Kb |
| Document Language | English |
Enhanced Product. AD7980-EP. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol Min Typ Max Unit. 500µA. Y% VIO1. X% VIO1. tDELAY. V 2
Model Line for this Datasheet
Text Version of Document
link to page 5 link to page 5
Enhanced Product AD7980-EP TIMING SPECIFICATIONS
−55°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 500 710 ns Acquisition Time tACQ 290 ns Time Between Conversions tCYC 1000 ns CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK ns VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK ns VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns
500µA I Y% VIO1 OL X% VIO1 tDELAY tDELAY V 2 2 TO SDO 1.4V IH VIH 2 2 C V V L IL IL 20pF 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2 3
500µA I
00
2MINIMUM V
00
OH
4-
IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
4- 30
SPECIFICATIONS IN TABLE 3.
30 09 09 Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. A | Page 5 of 12 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM EXAMPLE GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
Enhanced Product AD7980-EP TIMING SPECIFICATIONS
−55°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 500 710 ns Acquisition Time tACQ 290 ns Time Between Conversions tCYC 1000 ns CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK ns VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK ns VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 3 V 10 ns VIO Above 2.3 V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 15 ns
500µA I Y% VIO1 OL X% VIO1 tDELAY tDELAY V 2 2 TO SDO 1.4V IH VIH 2 2 C V V L IL IL 20pF 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2 3
500µA I
00
2MINIMUM V
00
OH
4-
IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
4- 30
SPECIFICATIONS IN TABLE 3.
30 09 09 Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. A | Page 5 of 12 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM EXAMPLE GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
