Datasheet ADA8282 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Radar Receive Path AFE: 4-Channel LNA and PGA |
| Pages / Page | 21 / 6 — ADA8282. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. SET. … |
| File Format / Size | PDF / 517 Kb |
| Document Language | English |
ADA8282. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. SET. +INA 1. 24 +OUTA. –INA 2. 23 –OUTA. +INB 3. 22 +OUTB. –INB 4. 21 –OUTB
Model Line for this Datasheet
Text Version of Document
ADA8282 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D D O I LK SET D E O AV SD SD CS SC R VI AV 32 31 30 29 28 27 26 25 +INA 1 24 +OUTA –INA 2 23 –OUTA +INB 3 22 +OUTB ADA8282 –INB 4 21 –OUTB +INC 5 TOP VIEW 20 +OUTC (Not to Scale) –INC 6 19 –OUTC +IND 7 18 +OUTD –IND 8 17 –OUTD 9 10 11 12 13 14 15 16 D D D NIC NIC NIC NIC NIC NIC D AV AV NOTES 1. NIC = NO INTERNAL CONNECTION.
2 00
2. TIE THE EXPOSED PAD ON THE BOTTOM SIDE OF THE
2-
PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.
1313 Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Pad. Tie the exposed pad on the bottom side of the package to the analog/digital ground plane. 1 +INA Positive LNA Analog Input for Channel A. 2 −INA Negative LNA Analog Input for Channel A. 3 +INB Positive LNA Analog Input for Channel B. 4 −INB Negative LNA Analog Input for Channel B. 5 +INC Positive LNA Analog Input for Channel C. 6 −INC Negative LNA Analog Input for Channel C. 7 +IND Positive LNA Analog Input for Channel D. 8 −IND Negative LNA Analog Input for Channel D. 9 AVDD 3.3 V Analog Supply. 10 NIC No Internal Connection. Leave this pin floating. 11 NIC No Internal Connection. Leave this pin floating. 12 NIC No Internal Connection. Leave this pin floating. 13 NIC No Internal Connection. Leave this pin floating. 14 NIC No Internal Connection. Leave this pin floating. 15 NIC No Internal Connection. Leave this pin floating. 16 AVDD 3.3 V Analog Supply. 17 −OUTD Negative Analog Output for Channel D. 18 +OUTD Positive Analog Output for Channel D. 19 −OUTC Negative Analog Output for Channel C. 20 +OUTC Positive Analog Output for Channel C. 21 −OUTB Negative Analog Output for Channel B. 22 +OUTB Positive Analog Output for Channel B. 23 −OUTA Negative Analog Output for Channel A. 24 +OUTA Positive Analog Output for Channel A. 25 AVDD 3.3 V Analog Supply. 26 VIO Digital Level Select for SPI and RESET. This pin can accept 1.8 V to 3.3 V. 27 RESET Reset Input. RESET overrides the SPI and powers down the device and returns all settings back to default. RESET is pulled to ground by default. A logic high triggers the reset. 28 SCLK Serial Clock. 29 CS Chip Select Bar. 30 SDI Serial Data Input. 31 SDO Serial Data Output. 32 AVDD 3.3 V Analog Supply. Rev. 0 | Page 6 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
2 00
2. TIE THE EXPOSED PAD ON THE BOTTOM SIDE OF THE
2-
PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.
1313 Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Pad. Tie the exposed pad on the bottom side of the package to the analog/digital ground plane. 1 +INA Positive LNA Analog Input for Channel A. 2 −INA Negative LNA Analog Input for Channel A. 3 +INB Positive LNA Analog Input for Channel B. 4 −INB Negative LNA Analog Input for Channel B. 5 +INC Positive LNA Analog Input for Channel C. 6 −INC Negative LNA Analog Input for Channel C. 7 +IND Positive LNA Analog Input for Channel D. 8 −IND Negative LNA Analog Input for Channel D. 9 AVDD 3.3 V Analog Supply. 10 NIC No Internal Connection. Leave this pin floating. 11 NIC No Internal Connection. Leave this pin floating. 12 NIC No Internal Connection. Leave this pin floating. 13 NIC No Internal Connection. Leave this pin floating. 14 NIC No Internal Connection. Leave this pin floating. 15 NIC No Internal Connection. Leave this pin floating. 16 AVDD 3.3 V Analog Supply. 17 −OUTD Negative Analog Output for Channel D. 18 +OUTD Positive Analog Output for Channel D. 19 −OUTC Negative Analog Output for Channel C. 20 +OUTC Positive Analog Output for Channel C. 21 −OUTB Negative Analog Output for Channel B. 22 +OUTB Positive Analog Output for Channel B. 23 −OUTA Negative Analog Output for Channel A. 24 +OUTA Positive Analog Output for Channel A. 25 AVDD 3.3 V Analog Supply. 26 VIO Digital Level Select for SPI and RESET. This pin can accept 1.8 V to 3.3 V. 27 RESET Reset Input. RESET overrides the SPI and powers down the device and returns all settings back to default. RESET is pulled to ground by default. A logic high triggers the reset. 28 SCLK Serial Clock. 29 CS Chip Select Bar. 30 SDI Serial Data Input. 31 SDO Serial Data Output. 32 AVDD 3.3 V Analog Supply. Rev. 0 | Page 6 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
