Datasheet HMC627ALP5E (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 0.5 dB LSB GaAs MMIC 6-Bit Digital Variable Gain Amplifier SMT, 50 MHz - 1 GHz |
| Pages / Page | 10 / 5 — HMC627ALP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL. VARIABLE GAIN AMPLIFIER, … |
| File Format / Size | PDF / 848 Kb |
| Document Language | English |
HMC627ALP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL. VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz. Serial Control Interface
Model Line for this Datasheet
Text Version of Document
HMC627ALP5E
v00.1212
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Serial Control Interface
The HMC627ALP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S T is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires M clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. L - S When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded asynchronously with paral el digital inputs (D0-D5). When Le is high, 6-bit paral el data is transferred to the attenuator. ITA For all modes of operations, the DVGA state will stay constant while LE is kept low. IG S - D R IE LIF P M IN A A LE G B Parameter Typ. IA Min. serial period, t 100 ns
Timing Diagram (Latched Parallel Mode)
SCK R Control set-up time, t 20 ns CS A Control hold-time, t 20 ns CH V LE setup-time, t 10 ns LN Min. LE pulse width, t 10 ns LEW Min LE pulse spacing, t 630 ns LES Serial clock hold-time from LE, t 10 ns CKN Hold Time, t 0 ns PH. Latch Enable Minimum Width, t 10 ns LEN Setup Time, t 2 ns PS
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note:
The paral el mode is enabled when P/S is set to low.
Direct Parallel Mode
- The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode
- The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m
5
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 o pplic r a atio pp n S s u @ p h por ittti : Pte ho.c n o e m : 1-800-ANALOG-D
v00.1212
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Serial Control Interface
The HMC627ALP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S T is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires M clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. L - S When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded asynchronously with paral el digital inputs (D0-D5). When Le is high, 6-bit paral el data is transferred to the attenuator. ITA For all modes of operations, the DVGA state will stay constant while LE is kept low. IG S - D R IE LIF P M IN A A LE G B Parameter Typ. IA Min. serial period, t 100 ns
Timing Diagram (Latched Parallel Mode)
SCK R Control set-up time, t 20 ns CS A Control hold-time, t 20 ns CH V LE setup-time, t 10 ns LN Min. LE pulse width, t 10 ns LEW Min LE pulse spacing, t 630 ns LES Serial clock hold-time from LE, t 10 ns CKN Hold Time, t 0 ns PH. Latch Enable Minimum Width, t 10 ns LEN Setup Time, t 2 ns PS
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note:
The paral el mode is enabled when P/S is set to low.
Direct Parallel Mode
- The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner.
Latched Parallel Mode
- The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m
5
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 o pplic r a atio pp n S s u @ p h por ittti : Pte ho.c n o e m : 1-800-ANALOG-D
