Datasheet STM32F103xC, STM32F103xD, STM32F103xE (STMicroelectronics) - 3

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STM32F103xC, STM32F103xD, STM32F103xE Contents
2.3.29 Serial wire JTAG debug port (SWJ-DP) . 24 2.3.30 Embedded Trace Macrocell™ . 24
3 Pinouts and pin descriptions . 25 4 Memory mapping . 40 5 Electrical characteristics . 41
5.1 Parameter conditions . 41 5.1.1 Minimum and maximum values . 41 5.1.2 Typical values . 41 5.1.3 Typical curves . 41 5.1.4 Loading capacitor . 41 5.1.5 Pin input voltage . 41 5.1.6 Power supply scheme . 42 5.1.7 Current consumption measurement . 42 5.2 Absolute maximum ratings . 43 5.3 Operating conditions . 44 5.3.1 General operating conditions . 44 5.3.2 Operating conditions at power-up / power-down . 45 5.3.3 Embedded reset and power control block characteristics . 45 5.3.4 Embedded reference voltage . 46 5.3.5 Supply current characteristics . 46 5.3.6 External clock source characteristics . 58 5.3.7 Internal clock source characteristics . 62 5.3.8 PLL characteristics . 64 5.3.9 Memory characteristics . 64 5.3.10 FSMC characteristics . 66 5.3.11 EMC characteristics . 86 5.3.12 Absolute maximum ratings (electrical sensitivity) . 87 5.3.13 I/O current injection characteristics . 88 5.3.14 I/O port characteristics . 89 5.3.15 NRST pin characteristics . 94 5.3.16 TIM timer characteristics . 95 5.3.17 Communications interfaces . 96 5.3.18 CAN (controller area network) interface . 106 5.3.19 12-bit ADC characteristics . 106 DS5792 Rev 13 3/143 4 Document Outline Table 1. Device summary 1 Introduction 2 Description 2.1 Device overview Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram Figure 2. Clock tree 2.2 Full compatibility throughout the family Table 3. STM32F103xx family 2.3 Overview 2.3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM 2.3.2 Embedded Flash memory 2.3.3 CRC (cyclic redundancy check) calculation unit 2.3.4 Embedded SRAM 2.3.5 FSMC (flexible static memory controller) 2.3.6 LCD parallel interface 2.3.7 Nested vectored interrupt controller (NVIC) 2.3.8 External interrupt/event controller (EXTI) 2.3.9 Clocks and startup 2.3.10 Boot modes 2.3.11 Power supply schemes 2.3.12 Power supply supervisor 2.3.13 Voltage regulator 2.3.14 Low-power modes 2.3.15 DMA 2.3.16 RTC (real-time clock) and backup registers 2.3.17 Timers and watchdogs Table 4. High-density timer feature comparison 2.3.18 I²C bus 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 2.3.20 Serial peripheral interface (SPI) 2.3.21 Inter-integrated sound (I2S) 2.3.22 SDIO 2.3.23 Controller area network (CAN) 2.3.24 Universal serial bus (USB) 2.3.25 GPIOs (general-purpose inputs/outputs) 2.3.26 ADC (analog to digital converter) 2.3.27 DAC (digital-to-analog converter) 2.3.28 Temperature sensor 2.3.29 Serial wire JTAG debug port (SWJ-DP) 2.3.30 Embedded Trace Macrocell™ 3 Pinouts and pin descriptions Figure 3. STM32F103xC/D/E BGA144 ballout Figure 4. STM32F103xC/D/E performance line BGA100 ballout Figure 5. STM32F103xC/D/E performance line LQFP144 pinout Figure 6. STM32F103xC/D/E performance line LQFP100 pinout Figure 7. STM32F103xC/D/E performance line LQFP64 pinout Figure 8. STM32F103xC/D/E performance line WLCSP64 ballout, ball side Table 5. High-density STM32F103xC/D/E pin definitions Table 6. FSMC pin definition 4 Memory mapping Figure 9. Memory map 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage Figure 10. Pin loading conditions Figure 11. Pin input voltage 5.1.6 Power supply scheme Figure 12. Power supply scheme 5.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme 5.2 Absolute maximum ratings Table 7. Voltage characteristics Table 8. Current characteristics Table 9. Thermal characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions 5.3.2 Operating conditions at power-up / power-down Table 11. Operating conditions at power-up / power-down 5.3.3 Embedded reset and power control block characteristics Table 12. Embedded reset and power control block characteristics 5.3.4 Embedded reference voltage Table 13. Embedded internal reference voltage 5.3.5 Supply current characteristics Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Table 15. Maximum current consumption in Run mode, code with data processing running from RAM Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)- code with data processing running from RAM, peripherals disabled Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Table 17. Typical and maximum current consumptions in Stop and Standby modes Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values Table 18. Typical current consumption in Run mode, code with data processing running from Flash Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Table 20. Peripheral current consumption 5.3.6 External clock source characteristics Table 21. High-speed external user clock characteristics Table 22. Low-speed external user clock characteristics Figure 20. High-speed external clock source AC timing diagram Figure 21. Low-speed external clock source AC timing diagram Table 23. HSE 4-16 MHz oscillator characteristics Figure 22. Typical application with an 8 MHz crystal Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 23. Typical application with a 32.768 kHz crystal 5.3.7 Internal clock source characteristics Table 25. HSI oscillator characteristics Table 26. LSI oscillator characteristics Table 27. Low-power mode wakeup timings 5.3.8 PLL characteristics Table 28. PLL characteristics 5.3.9 Memory characteristics Table 29. Flash memory characteristics Table 30. Flash memory endurance and data retention 5.3.10 FSMC characteristics Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms Table 33. Asynchronous multiplexed PSRAM/NOR read timings Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms Table 34. Asynchronous multiplexed PSRAM/NOR write timings Figure 28. Synchronous multiplexed NOR/PSRAM read timings Table 35. Synchronous multiplexed NOR/PSRAM read timings Figure 29. Synchronous multiplexed PSRAM write timings Table 36. Synchronous multiplexed PSRAM write timings Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings Table 37. Synchronous non-multiplexed NOR/PSRAM read timings Figure 31. Synchronous non-multiplexed PSRAM write timings Table 38. Synchronous non-multiplexed PSRAM write timings Figure 32. PC Card/CompactFlash controller waveforms for common memory read access Figure 33. PC Card/CompactFlash controller waveforms for common memory write access Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access Table 39. Switching characteristics for PC Card/CF read and write cycles Figure 38. NAND controller waveforms for read access Figure 39. NAND controller waveforms for write access Figure 40. NAND controller waveforms for common memory read access Figure 41. NAND controller waveforms for common memory write access Table 40. Switching characteristics for NAND Flash read and write cycles 5.3.11 EMC characteristics Table 41. EMS characteristics Table 42. EMI characteristics 5.3.12 Absolute maximum ratings (electrical sensitivity) Table 43. ESD absolute maximum ratings Table 44. Electrical sensitivities 5.3.13 I/O current injection characteristics Table 45. I/O current injection susceptibility 5.3.14 I/O port characteristics Table 46. I/O static characteristics Figure 42. Standard I/O input characteristics - CMOS port Figure 43. Standard I/O input characteristics - TTL port Figure 44. 5 V tolerant I/O input characteristics - CMOS port Figure 45. 5 V tolerant I/O input characteristics - TTL port Table 47. Output voltage characteristics Table 48. I/O AC characteristics Figure 46. I/O AC characteristics definition 5.3.15 NRST pin characteristics Table 49. NRST pin characteristics Figure 47. Recommended NRST pin protection 5.3.16 TIM timer characteristics Table 50. TIMx characteristics 5.3.17 Communications interfaces Table 51. I2C characteristics Figure 48. I2C bus AC waveforms and measurement circuit Table 52. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) Table 53. SPI characteristics Figure 49. SPI timing diagram - slave mode and CPHA = 0 Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) Figure 51. SPI timing diagram - master mode(1) Table 54. I2S characteristics Figure 52. I2S slave timing diagram (Philips protocol)(1) Figure 53. I2S master timing diagram (Philips protocol)(1) Figure 54. SDIO high-speed mode Figure 55. SD default mode Table 55. SD / MMC characteristics Table 56. USB startup time Table 57. USB DC electrical characteristics Figure 56. USB timings: definition of data signal rise and fall time Table 58. USB: full-speed electrical characteristics 5.3.18 CAN (controller area network) interface 5.3.19 12-bit ADC characteristics Table 59. ADC characteristics Table 60. RAIN max for fADC = 14 MHz Table 61. ADC accuracy - limited test conditions Table 62. ADC accuracy Figure 57. ADC accuracy characteristics Figure 58. Typical connection diagram using the ADC Figure 59. Power supply and reference decoupling (VREF+ not connected to VDDA) Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA) 5.3.20 DAC electrical specifications Table 63. DAC characteristics Figure 61. 12-bit buffered /non-buffered DAC 5.3.21 Temperature sensor characteristics Table 64. TS characteristics 6 Package information 6.1 LFBGA144 package information Figure 62. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint Table 66. LFBGA144 recommended PCB design rules (0.8 mm pitch BGA) Figure 64. LFBGA144 marking example (package top view) 6.2 LFBGA100 package information Figure 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data Figure 66. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprintoutline Table 68. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Figure 67. LFBGA100 marking example (package top view) 6.3 WLCSP64 package information Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch) 6.4 LQFP144 package information Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline Table 71. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint Figure 72. LQFP144 marking example (package top view) 6.5 LQFP100 package information Figure 73. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data Figure 74. LQFP100 recommended footprint Figure 75. LQFP100 marking example (package top view) 6.6 LQFP64 package information Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data Figure 77. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint Figure 78. LQFP64 marking example (package top view) 6.7 Thermal characteristics Table 74. Package thermal characteristics 6.7.1 Reference document 6.7.2 Selecting the product temperature range Figure 79. LQFP100 PD max vs. TA 7 Ordering information Table 75. Ordering information scheme 8 Revision history