Datasheet HT68F001, HT68F0012 (Holtek) - 3
| Manufacturer | Holtek |
| Description | Cost-Effective Flash MCU |
| Pages / Page | 56 / 3 — HT68F001/HT68F0012. Cost-Effective Flash MCU. Oscillators .. 22. … |
| File Format / Size | PDF / 3.3 Mb |
| Document Language | English |
HT68F001/HT68F0012. Cost-Effective Flash MCU. Oscillators .. 22. Operating Modes and System Clocks ... 23
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HT68F001/HT68F0012 HT68F001/HT68F0012 Cost-Effective Flash MCU Cost-Effective Flash MCU
Look-u� Tab�e Registe�s – TBLP ... 20 Status Registe� – ST�TUS .. 20
Oscillators .. 22
Osci��ato� Ove�view ... 22 System Clock Configurations ... 22 Inte�na� 32kHz Osci��ato� – LIRC .. 23 Inte�na� 512kHz Osci��ato� – IRC ... 23
Operating Modes and System Clocks ... 23
System C�ocks ... 23 System O�e�ation Modes .. 24 Standby Cu��ent Conside�ations .. 25 Wake-u� .. 25
Watchdog Timer ... 26
Watchdog Time� C�ock Sou�ce .. 26 Watchdog Time� Cont�o� Registe� ... 26 Watchdog Time� O�e�ation ... 2�
Reset and Initialisation .. 29
Reset Functions .. 29 Reset Initia� Conditions .. 30
Input/Output Ports .. 31
Pu��-high Resisto�s .. 31 Po�t � Wake-u� ... 31 I/O Po�t Cont�o� Registe�s ... 32 I/O Pin St�uctu�es .. 32 P�og�amming Conside�ations ... 33
Timer/Event Counter ... 34
Time�/Event Counte� Registe�s – TMR� TMRC ... 34 Time� Mode ... 36 Event Counte� Mode ... 36 Pu�se Width Ca�tu�e Mode ... 36
Interrupts .. 37
Inte��u�t Registe�s ... 3� Inte��u�t O�e�ation .. 3� Time Base Inte��u�t ... 39 Inte��u�t Wake-u� Function ... 39 P�og�amming Conside�ations .. 40
Application Circuits ... 40 Instruction Set .. 41
Int�oduction ... 41 Inst�uction Timing .. 41 Moving and T�ansfe��ing Data ... 41 ��ithmetic O�e�ations .. 41 Logica� and Rotate O�e�ation ... 42 Rev. 1.20 2 ���i� 1�� 201� Rev. 1.20 3 ���i� 1�� 201� Document Outline Features CPU Features Peripheral Features General Description Selection Table Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics Operating Voltage Characteristics Operating Current Characteristics Standby Current Characteristics A.C. Characteristics Low Speed Internal Oscillator Characteristics (LIRC) – HT68F001 Low Speed Internal Oscillator Characteristics (IRC) – HT68F0012 System Start Up Time Characteristics Input/Output Characteristics Power on Reset Characteristics System Architecture Clocking and Pipelining Program Counter Stack Arithmetic and Logic Unit – ALU Flash Program Memory Structure Special Vectors Look-up Table Table Program Example In Circuit Programming – ICP On-Chip Debug Support – OCDS Data Memory Structure General Purpose Data Memory Special Purpose Data Memory Special Function Register Description Indirect Addressing Registers – IAR0 Memory Pointers – MP0 Accumulator – ACC Program Counter Low Register – PCL Look-up Table Registers – TBLP Status Register – STATUS Oscillators Oscillator Overview System Clock Configurations Internal 32kHz Oscillator – LIRC Internal 512kHz Oscillator – IRC Operating Modes and System Clocks System Clocks System Operation Modes Standby Current Considerations Wake-up Watchdog Timer Watchdog Timer Clock Source Watchdog Timer Control Register Watchdog Timer Operation Reset and Initialisation Reset Functions Reset Initial Conditions Input/Output Ports Pull-high Resistors Port A Wake-up I/O Port Control Registers I/O Pin Structures Programming Considerations Timer/Event Counter Timer/Event Counter Registers – TMR, TMRC Timer Mode Event Counter Mode Pulse Width Capture Mode Interrupts Interrupt Registers Interrupt Operation Time Base Interrupt Interrupt Wake-up Function Programming Considerations Application Circuits Instruction Set Introduction Instruction Timing Moving and Transferring Data Arithmetic Operations Logical and Rotate Operation Branches and Control Transfer Bit Operations Table Read Operations Other Operations Instruction Set Summary Table Conventions Instruction Definition Package Information 8-pin SOP (150mil) Outline Dimensions
HT68F001/HT68F0012 HT68F001/HT68F0012 Cost-Effective Flash MCU Cost-Effective Flash MCU
Look-u� Tab�e Registe�s – TBLP ... 20 Status Registe� – ST�TUS .. 20
Oscillators .. 22
Osci��ato� Ove�view ... 22 System Clock Configurations ... 22 Inte�na� 32kHz Osci��ato� – LIRC .. 23 Inte�na� 512kHz Osci��ato� – IRC ... 23
Operating Modes and System Clocks ... 23
System C�ocks ... 23 System O�e�ation Modes .. 24 Standby Cu��ent Conside�ations .. 25 Wake-u� .. 25
Watchdog Timer ... 26
Watchdog Time� C�ock Sou�ce .. 26 Watchdog Time� Cont�o� Registe� ... 26 Watchdog Time� O�e�ation ... 2�
Reset and Initialisation .. 29
Reset Functions .. 29 Reset Initia� Conditions .. 30
Input/Output Ports .. 31
Pu��-high Resisto�s .. 31 Po�t � Wake-u� ... 31 I/O Po�t Cont�o� Registe�s ... 32 I/O Pin St�uctu�es .. 32 P�og�amming Conside�ations ... 33
Timer/Event Counter ... 34
Time�/Event Counte� Registe�s – TMR� TMRC ... 34 Time� Mode ... 36 Event Counte� Mode ... 36 Pu�se Width Ca�tu�e Mode ... 36
Interrupts .. 37
Inte��u�t Registe�s ... 3� Inte��u�t O�e�ation .. 3� Time Base Inte��u�t ... 39 Inte��u�t Wake-u� Function ... 39 P�og�amming Conside�ations .. 40
Application Circuits ... 40 Instruction Set .. 41
Int�oduction ... 41 Inst�uction Timing .. 41 Moving and T�ansfe��ing Data ... 41 ��ithmetic O�e�ations .. 41 Logica� and Rotate O�e�ation ... 42 Rev. 1.20 2 ���i� 1�� 201� Rev. 1.20 3 ���i� 1�� 201� Document Outline Features CPU Features Peripheral Features General Description Selection Table Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics Operating Voltage Characteristics Operating Current Characteristics Standby Current Characteristics A.C. Characteristics Low Speed Internal Oscillator Characteristics (LIRC) – HT68F001 Low Speed Internal Oscillator Characteristics (IRC) – HT68F0012 System Start Up Time Characteristics Input/Output Characteristics Power on Reset Characteristics System Architecture Clocking and Pipelining Program Counter Stack Arithmetic and Logic Unit – ALU Flash Program Memory Structure Special Vectors Look-up Table Table Program Example In Circuit Programming – ICP On-Chip Debug Support – OCDS Data Memory Structure General Purpose Data Memory Special Purpose Data Memory Special Function Register Description Indirect Addressing Registers – IAR0 Memory Pointers – MP0 Accumulator – ACC Program Counter Low Register – PCL Look-up Table Registers – TBLP Status Register – STATUS Oscillators Oscillator Overview System Clock Configurations Internal 32kHz Oscillator – LIRC Internal 512kHz Oscillator – IRC Operating Modes and System Clocks System Clocks System Operation Modes Standby Current Considerations Wake-up Watchdog Timer Watchdog Timer Clock Source Watchdog Timer Control Register Watchdog Timer Operation Reset and Initialisation Reset Functions Reset Initial Conditions Input/Output Ports Pull-high Resistors Port A Wake-up I/O Port Control Registers I/O Pin Structures Programming Considerations Timer/Event Counter Timer/Event Counter Registers – TMR, TMRC Timer Mode Event Counter Mode Pulse Width Capture Mode Interrupts Interrupt Registers Interrupt Operation Time Base Interrupt Interrupt Wake-up Function Programming Considerations Application Circuits Instruction Set Introduction Instruction Timing Moving and Transferring Data Arithmetic Operations Logical and Rotate Operation Branches and Control Transfer Bit Operations Table Read Operations Other Operations Instruction Set Summary Table Conventions Instruction Definition Package Information 8-pin SOP (150mil) Outline Dimensions
