Datasheet ADN2892 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 3.3 V 4.25 Gb/s Limiting Amplifier |
| Pages / Page | 16 / 7 — Data Sheet. ADN2892. TYPICAL PERFORMANCE CHARACTERISTICS. 0.06. +95. … |
| Revision | C |
| File Format / Size | PDF / 458 Kb |
| Document Language | English |
Data Sheet. ADN2892. TYPICAL PERFORMANCE CHARACTERISTICS. 0.06. +95. 0.05. +25. ) (V E 0.04. AS LE. 0.03. 150mV/DIV. –40. AND RE. 0.02. TRIP
Model Line for this Datasheet
Text Version of Document
Data Sheet ADN2892 TYPICAL PERFORMANCE CHARACTERISTICS 0.06 +95 C 0.05 +25 C ) (V E 0.04 AS LE 0.03 150mV/DIV –40 C AND RE 0.02 TRIP –40 C DEASSERTION 0.01 +25 C +95 C ASSERTION
04986-012
50ps/DIV 0
04986-026
1k 10k 100k RTH ( )
Figure 3. Eye of ADN2892 at 25°C, 4.25 Gbps, and 10 mV Input Figure 6. LOS Trip and Release vs. RTH at 4.25 Gbps
8 7 1GBPS (dB) 6 IS S E R 5 4.25GBPS E T S 4 150mV/DIV 3 TRICAL HY C E 2 L E 1
04986-023
50ps/DIV 0
04986-027
1k 10k 100k RTH ( )
Figure 4. Eye of ADN2892 at 95°C, 4.25 Gbps, and 10 mV Input Figure 7. LOS Electrical Hysteresis vs. RTH at 25°C
16 14 12 10 LES P 8 M 150mV/DIV SA 6 4 2
04986-010
0
04986-024
200ps/DIV 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 ELECTRICAL HYSTERESIS (dB)
Figure 5. Eye of ADN2892 at 25°C, 1.063 Gbps, and 10 mV Input (BW_SEL = 0) Figure 8. Sample Lot Distribution—Worst-Case Condition: Conditions = 4.25 Gbps, 100 kΩ at −40°C, 3.6 V Rev. C | Page 7 of 16 Document Outline Features Applications General Description Functional Block Diagram Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Limiting Amplifier Input Buffer CML Output Buffer Loss-of-Signal (LOS) Detector Received Signal Strength Indicator (RSSI) Squelch Mode BW_SEL (Bandwidth Selection) Mode LOS_INV (Lose of Signal_Invert) Mode Applications Information PCB Design Guidelines Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP Pad Coating and Pb-Free Soldering Outline Dimensions Ordering Guide
04986-012
50ps/DIV 0
04986-026
1k 10k 100k RTH ( )
Figure 3. Eye of ADN2892 at 25°C, 4.25 Gbps, and 10 mV Input Figure 6. LOS Trip and Release vs. RTH at 4.25 Gbps
8 7 1GBPS (dB) 6 IS S E R 5 4.25GBPS E T S 4 150mV/DIV 3 TRICAL HY C E 2 L E 1
04986-023
50ps/DIV 0
04986-027
1k 10k 100k RTH ( )
Figure 4. Eye of ADN2892 at 95°C, 4.25 Gbps, and 10 mV Input Figure 7. LOS Electrical Hysteresis vs. RTH at 25°C
16 14 12 10 LES P 8 M 150mV/DIV SA 6 4 2
04986-010
0
04986-024
200ps/DIV 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 ELECTRICAL HYSTERESIS (dB)
Figure 5. Eye of ADN2892 at 25°C, 1.063 Gbps, and 10 mV Input (BW_SEL = 0) Figure 8. Sample Lot Distribution—Worst-Case Condition: Conditions = 4.25 Gbps, 100 kΩ at −40°C, 3.6 V Rev. C | Page 7 of 16 Document Outline Features Applications General Description Functional Block Diagram Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Limiting Amplifier Input Buffer CML Output Buffer Loss-of-Signal (LOS) Detector Received Signal Strength Indicator (RSSI) Squelch Mode BW_SEL (Bandwidth Selection) Mode LOS_INV (Lose of Signal_Invert) Mode Applications Information PCB Design Guidelines Output Buffer Power Supply and Ground Planes PCB Layout Soldering Guidelines for the LFCSP Pad Coating and Pb-Free Soldering Outline Dimensions Ordering Guide
