Datasheet ADN2890 (Analog Devices)

3.3 V 2.7 Gb/s Limiting Amplifier Data Sheet ADN2890 FEATURES GENERAL DESCRIPTION SFP reference design available
The ADN2890 is a high gain, limiting amplifier optimized for
Input sensitivity: 3 mV p-p
use in SONET, Gigabit Ethernet (GbE), and Fibre Channel
80 ps rise/fall times
optical receivers that accept input levels of up to 2.0 V p-p
CML outputs: 700 mV p-p differential
differential and have 3 mV p-p differential input sensitivity. The
Programmable LOS detector: 2 mV to 13 mV
ADN2890 provides the receiver functions of quantization and
Rx signal strength indicator (RSSI):
loss of signal (LOS) detection. The ADN2890 can easily operate
SFF-8472 compliant average power measurement
at up to 3.2 Gb/s to support LX4 transceivers.
Single-supply operation: 3.3 V
The limiting amplifier also measures average received power
Low power dissipation: 130 mW
based on a direct measurement of the photodiode current with
Available in space-saving 3 mm × 3 mm 16-lead LFCSP
better than 1 dB of accuracy over the entire input range of the
APPLICATIONS
receiver. This eliminates the need for external average Rx power
SFP/SFF/GBIC optical transceivers
detection circuitry in SFF-8472 compliant optical transceivers.
OC-3/12/48, GbE, Fibre Channel receivers
The ADN2890 limiting amplifier operates from a single 3.3 V
10GBASE-LX4 transceivers
supply, has low power dissipation, and is available in a space-
WDM transponders
saving 3 mm × 3 mm 16-lead lead frame chip scale package

(LFCSP).
FUNCTIONAL BLOCK DIAGRAM AVCC AVEE DRVCC DRVEE DRVCC ADN2890 50
Ω
50
Ω
CF RF PIN OUTP ADN2880 NIN OUTN 50
Ω
50
Ω
+V VREF 3k
Ω
10k
Ω
LOS PD_VCC RSSI/LOS DETECTOR RSSI_OUT ADuC7020 PD_CATHODE CAZ1 CAZ2 THRADJ SQUELCH 0.01
µ
F
04509-0-001 Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMAMP Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes PCB Layout Soldering Guidelines for Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE NOTES