Datasheet ADL5306 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 60 dB-RANGE (100 nA-100 µA) Low-Cost Logarithmic Converter |
| Pages / Page | 16 / 5 — COMM COMM COMM COMM. NC 1. 12 VOUT. VREF 2. 11 SCAL. ADL5306. IREF 3. 10 … |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
COMM COMM COMM COMM. NC 1. 12 VOUT. VREF 2. 11 SCAL. ADL5306. IREF 3. 10 BFIN. INPT 4. 9 VLOG. VSUM VNEG VNEG VPOS. 03727-0-002
Model Line for this Datasheet
Text Version of Document
link to page 11 ADL5306 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
COMM COMM COMM COMM 16 15 14 13 NC 1 12 VOUT VREF 2 11 SCAL ADL5306 IREF 3 10 BFIN INPT 4 9 VLOG 5 6 7 8 VSUM VNEG VNEG VPOS 03727-0-002
Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP)
Table 3. Pin Function Descriptions Pin No. Mnemonic Function
1 NC N/A 2 VREF Reference Output Voltage of 2.5 V. 3 IREF Accepts (Sinks) Reference Current IREF. 4 INPT Accepts (Sinks) Photodiode Current IPD. Usually connected to photodiode anode such that photocurrent flows into INPT. 5 VSUM Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. 6, 7 VNEG Optional Negative Supply, VN. This pin is usually grounded; for details of usage, see the Applications section. 8 VPOS Positive Supply, ( VP – VN ) ≤ 11 V. 9 VLOG Output of the Logarithmic Front End. 10 BFIN Buffer Amplifier Noninverting Input. 11 SCAL Buffer Amplifier Inverting Input. 12 VOUT Buffer Output. 13–16 COMM Analog Ground. Rev. 0 | Page 5 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS GENERAL STRUCTURE THEORY MANAGING INTERCEPT AND SLOPE RESPONSE TIME AND NOISE CONSIDERATIONS APPLICATIONS USING A NEGATIVE SUPPLY CHARACTERIZATION METHODS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
COMM COMM COMM COMM 16 15 14 13 NC 1 12 VOUT VREF 2 11 SCAL ADL5306 IREF 3 10 BFIN INPT 4 9 VLOG 5 6 7 8 VSUM VNEG VNEG VPOS 03727-0-002
Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP)
Table 3. Pin Function Descriptions Pin No. Mnemonic Function
1 NC N/A 2 VREF Reference Output Voltage of 2.5 V. 3 IREF Accepts (Sinks) Reference Current IREF. 4 INPT Accepts (Sinks) Photodiode Current IPD. Usually connected to photodiode anode such that photocurrent flows into INPT. 5 VSUM Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. 6, 7 VNEG Optional Negative Supply, VN. This pin is usually grounded; for details of usage, see the Applications section. 8 VPOS Positive Supply, ( VP – VN ) ≤ 11 V. 9 VLOG Output of the Logarithmic Front End. 10 BFIN Buffer Amplifier Noninverting Input. 11 SCAL Buffer Amplifier Inverting Input. 12 VOUT Buffer Output. 13–16 COMM Analog Ground. Rev. 0 | Page 5 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS GENERAL STRUCTURE THEORY MANAGING INTERCEPT AND SLOPE RESPONSE TIME AND NOISE CONSIDERATIONS APPLICATIONS USING A NEGATIVE SUPPLY CHARACTERIZATION METHODS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
