Datasheet AD7711A (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | LC2MOS Signal Conditioning ADC with RTD Current Source |
| Pages / Page | 28 / 5 — AD7711A. TIMING CHARACTERISTICS1, 2 (DVDD = +5 V. 5%; AVDD = +5 V or +10 … |
| File Format / Size | PDF / 396 Kb |
| Document Language | English |
AD7711A. TIMING CHARACTERISTICS1, 2 (DVDD = +5 V. 5%; AVDD = +5 V or +10 V3,. 5%; VSS = 0 V or –5 V. 10%; AGND = DGND
Model Line for this Datasheet
Text Version of Document
AD7711A TIMING CHARACTERISTICS1, 2 (DVDD = +5 V
6
5%; AVDD = +5 V or +10 V3,
6
5%; VSS = 0 V or –5 V
6
10%; AGND = DGND = 0 V; fCLKIN = 10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments
f 4, 5 CLK IN Master Clock Frequency: Crystal Oscillator or Externally 400 kHz min Supplied for Specified Performance 10 MHz max AV
2
DD = 5 V ± 5% 8 MHz max AVDD = 5.25 V to 10.5 V tCLK IN LO 0.4 ¥ tCLK IN ns min Master Clock Input Low Time. tCLK IN = 1/fCLK IN tCLK IN HI 0.4 ¥ tCLK IN ns min Master Clock Input High Time t 6 r 50 ns max Digital Output Rise Time. Typically 20 ns t 6 f 50 ns max Digital Output Fall Time. Typically 20 ns t1 1000 ns min SYNC Pulse Width Self-Clocking Mode t2 0 ns min DRDY to RFS Setup Time t3 0 ns min DRDY to RFS Hold Time t4 2 ¥ tCLK IN ns min A0 to RFS Setup Time t5 0 ns min A0 to RFS Hold Time t6 4 ¥ tCLK IN + 20 ns max RFS Low to SCLK Falling Edge t 7 7 4 ¥ tCLK IN + 20 ns max Data Access Time (RFS Low to Data Valid) t 7 8 tCLK IN/2 ns min SCLK Falling Edge to Data Valid Delay tCLK IN/2 + 30 ns max t9 tCLK IN/2 ns nom SCLK High Pulse Width t10 3 ¥ tCLK IN/2 ns nom SCLK Low Pulse Width t14 50 ns min A0 to TFS Setup Time t15 0 ns min A0 to TFS Hold Time t16 4 ¥ tCLK IN + 20 ns max TFS to SCLK Falling Edge Delay Time t17 4 ¥ tCLK IN ns min TFS to SCLK Falling Edge Hold Time t18 0 ns min Data Valid to SCLK Setup Time t19 10 ns min Data Valid to SCLK Hold Time NOTES 1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 10 to 13. 3The AD7711A is specified with a 10 MHz clock for AVDD voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25 V and less than 10.5 V. 4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711A is not in STANDBY mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5The AD7711A is production tested with fCLK IN at 10 MHz (8 MHz for AVDD > 5.25 V). It is guaranteed by characterization to operate at 400 kHz. 6Specified using 10% and 90% points on waveform of interest. REV. D –5–
6
5%; AVDD = +5 V or +10 V3,
6
5%; VSS = 0 V or –5 V
6
10%; AGND = DGND = 0 V; fCLKIN = 10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments
f 4, 5 CLK IN Master Clock Frequency: Crystal Oscillator or Externally 400 kHz min Supplied for Specified Performance 10 MHz max AV
2
DD = 5 V ± 5% 8 MHz max AVDD = 5.25 V to 10.5 V tCLK IN LO 0.4 ¥ tCLK IN ns min Master Clock Input Low Time. tCLK IN = 1/fCLK IN tCLK IN HI 0.4 ¥ tCLK IN ns min Master Clock Input High Time t 6 r 50 ns max Digital Output Rise Time. Typically 20 ns t 6 f 50 ns max Digital Output Fall Time. Typically 20 ns t1 1000 ns min SYNC Pulse Width Self-Clocking Mode t2 0 ns min DRDY to RFS Setup Time t3 0 ns min DRDY to RFS Hold Time t4 2 ¥ tCLK IN ns min A0 to RFS Setup Time t5 0 ns min A0 to RFS Hold Time t6 4 ¥ tCLK IN + 20 ns max RFS Low to SCLK Falling Edge t 7 7 4 ¥ tCLK IN + 20 ns max Data Access Time (RFS Low to Data Valid) t 7 8 tCLK IN/2 ns min SCLK Falling Edge to Data Valid Delay tCLK IN/2 + 30 ns max t9 tCLK IN/2 ns nom SCLK High Pulse Width t10 3 ¥ tCLK IN/2 ns nom SCLK Low Pulse Width t14 50 ns min A0 to TFS Setup Time t15 0 ns min A0 to TFS Hold Time t16 4 ¥ tCLK IN + 20 ns max TFS to SCLK Falling Edge Delay Time t17 4 ¥ tCLK IN ns min TFS to SCLK Falling Edge Hold Time t18 0 ns min Data Valid to SCLK Setup Time t19 10 ns min Data Valid to SCLK Hold Time NOTES 1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 10 to 13. 3The AD7711A is specified with a 10 MHz clock for AVDD voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25 V and less than 10.5 V. 4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711A is not in STANDBY mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 5The AD7711A is production tested with fCLK IN at 10 MHz (8 MHz for AVDD > 5.25 V). It is guaranteed by characterization to operate at 400 kHz. 6Specified using 10% and 90% points on waveform of interest. REV. D –5–
