Datasheet ARG81800 (Allegro)
| Manufacturer | Allegro |
| Description | 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD |
| Pages / Page | 42 / 1 — ARG81800. 40 V, 500 mA / 1.0 A Synchronous Buck Regulators. with Ultralow … |
| File Format / Size | PDF / 4.0 Mb |
| Document Language | English |
ARG81800. 40 V, 500 mA / 1.0 A Synchronous Buck Regulators. with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
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ARG81800 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD FEATURES AND BENEFITS DESCRIPTION
• Automotive AEC-Q100 qualified The ARG81800 includes all the control and protection circuitry • Input operating voltage range: 3.5 to 36 V to produce a PWM regulator with ±1.5% output voltage □ Withstands surge voltages to 40 V for load dump accuracy, with ultralow quiescent current to enable “keepalive” • Low-Power (LP) mode—draws just 8 µA from V supply operation with minimal current draw from the supply IN while maintaining 3.3 or 5.0 V during very light load regulation. There are two versions of OUT • AUTO mode allows automatic transition between PWM the ARG81800 available, 500 mA and 1 A, so the physical size and LP mode based on load current of the power components can be optimized for lower current • Programmable PWM frequency (f systems, thus reducing PCB area and saving cost. PWM SW): 250 kHz to 2.4 MHz • PWM frequency dithering and controlled switch node switching frequency can be programmed over a wide range to slew rate reduce EMI/EMC signature balance efficiency, component sizing, and EMC performance. • CLK If V OUT allows interleaving and dithering of “downstream” IN decays and the duty cycle reaches its maximum, the regulators using their synchronization inputs ARG81800 will automatically fold back its PWM frequency • Interleaving minimizes input filter capacitor requirement to extend the duty cycle and maintain VOUT. and improves EMI/EMC performance The ARG81800 employs Low-Power (LP) mode to maintain • Synchronization of PWM frequency to external clock on the output voltage at no load or very light load conditions while SYNCIN pin drawing only micro-amps from VIN. The ARG81800 includes a • Adjustable output voltage: ±1.5% accuracy over PWM/AUTO control pin so the system can dynamically force operating temperature range (‒40°C to 150°C) either PWM or AUTO mode by setting this pin high or low, • Maximized duty cycle at low VIN improves dropout respectively. • Soft recovery from dropout condition If the SYNC • Adjustable soft-start time controls inrush current to IN pin is driven by an external clock, the ARG81800 will be forced into PWM mode and synchronize to the incoming accommodate a wide range of output capacitances clock. The ARG81800 adds frequency dithering to the SYNC • External compensation provides flexibility to tune the IN clock to reduce EMI/EMC. The ARG81800 provides a CLK system for maximum stability or fast transient response OUT pin so “downstream” regulators can be easily interleaved and Continued on next page... dithered via their synchronization inputs. Continued on next page...
APPLICATIONS
• Infotainment • Battery Powered Systems
PACKAGE:
• Navigation Systems • Industrial Systems 20-pin, 4 mm × 4 mm, • Instrument Clusters • Network and Telecom QFN (ES) with wettable flank • Audio Systems • Home Audio Not to scale • ADAS Applications • HVAC Systems 3.5 to 36 V
VIN BIAS
1 µF
GND BOOT PGND
0.1 µF 3.3 µH 3.3 V, 1 A
SW
301 kΩ
PWM/AUTO FB
20 µF
EN
95.3 kΩ
SYNCIN
4.7 pF 10 kΩ
PGOOD FSET CLKOUT
14.3 kΩ
COMP
fSW = 2.15 MHz
SS VREG
2.2 nF 68 pF 22 nF 4.7 µF 40.2 kΩ
Typical Application Diagram
ARG81800-DS June 11, 2019 MCO-0000676 Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing
• Automotive AEC-Q100 qualified The ARG81800 includes all the control and protection circuitry • Input operating voltage range: 3.5 to 36 V to produce a PWM regulator with ±1.5% output voltage □ Withstands surge voltages to 40 V for load dump accuracy, with ultralow quiescent current to enable “keepalive” • Low-Power (LP) mode—draws just 8 µA from V supply operation with minimal current draw from the supply IN while maintaining 3.3 or 5.0 V during very light load regulation. There are two versions of OUT • AUTO mode allows automatic transition between PWM the ARG81800 available, 500 mA and 1 A, so the physical size and LP mode based on load current of the power components can be optimized for lower current • Programmable PWM frequency (f systems, thus reducing PCB area and saving cost. PWM SW): 250 kHz to 2.4 MHz • PWM frequency dithering and controlled switch node switching frequency can be programmed over a wide range to slew rate reduce EMI/EMC signature balance efficiency, component sizing, and EMC performance. • CLK If V OUT allows interleaving and dithering of “downstream” IN decays and the duty cycle reaches its maximum, the regulators using their synchronization inputs ARG81800 will automatically fold back its PWM frequency • Interleaving minimizes input filter capacitor requirement to extend the duty cycle and maintain VOUT. and improves EMI/EMC performance The ARG81800 employs Low-Power (LP) mode to maintain • Synchronization of PWM frequency to external clock on the output voltage at no load or very light load conditions while SYNCIN pin drawing only micro-amps from VIN. The ARG81800 includes a • Adjustable output voltage: ±1.5% accuracy over PWM/AUTO control pin so the system can dynamically force operating temperature range (‒40°C to 150°C) either PWM or AUTO mode by setting this pin high or low, • Maximized duty cycle at low VIN improves dropout respectively. • Soft recovery from dropout condition If the SYNC • Adjustable soft-start time controls inrush current to IN pin is driven by an external clock, the ARG81800 will be forced into PWM mode and synchronize to the incoming accommodate a wide range of output capacitances clock. The ARG81800 adds frequency dithering to the SYNC • External compensation provides flexibility to tune the IN clock to reduce EMI/EMC. The ARG81800 provides a CLK system for maximum stability or fast transient response OUT pin so “downstream” regulators can be easily interleaved and Continued on next page... dithered via their synchronization inputs. Continued on next page...
APPLICATIONS
• Infotainment • Battery Powered Systems
PACKAGE:
• Navigation Systems • Industrial Systems 20-pin, 4 mm × 4 mm, • Instrument Clusters • Network and Telecom QFN (ES) with wettable flank • Audio Systems • Home Audio Not to scale • ADAS Applications • HVAC Systems 3.5 to 36 V
VIN BIAS
1 µF
GND BOOT PGND
0.1 µF 3.3 µH 3.3 V, 1 A
SW
301 kΩ
PWM/AUTO FB
20 µF
EN
95.3 kΩ
SYNCIN
4.7 pF 10 kΩ
PGOOD FSET CLKOUT
14.3 kΩ
COMP
fSW = 2.15 MHz
SS VREG
2.2 nF 68 pF 22 nF 4.7 µF 40.2 kΩ
Typical Application Diagram
ARG81800-DS June 11, 2019 MCO-0000676 Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing
