Datasheet 48L640 (Microchip) - 14
| Manufacturer | Microchip |
| Description | 64-Kbit SPI Serial EERAM |
| Pages / Page | 40 / 14 — 48L640. TABLE 6-2:. BLOCK WRITE-PROTECT BITS. STATUS Register Bits [3:2]. … |
| File Format / Size | PDF / 563 Kb |
| Document Language | English |
48L640. TABLE 6-2:. BLOCK WRITE-PROTECT BITS. STATUS Register Bits [3:2]. Protected Address Range. Level. BP1. BP0. 6.2
Model Line for this Datasheet
Text Version of Document
link to page 12 link to page 12 link to page 12 link to page 12
48L640 TABLE 6-2: BLOCK WRITE-PROTECT BITS STATUS Register Bits [3:2] Protected Address Range Level BP1 BP0 48L640
0 0 0 None 1 0 1 1800-1FFF 2 1 0 1000-1FFF 3 1 1 0000-1FFF
6.2 Write Enable Latch
A logic ‘1’ bit indicates that the device is currently busy performing an SRAM to EEPROM transfer or EEPROM Enabling and disabling writing to the STATUS register to SRAM restore operation. During this time, only the and the SRAM array is accomplished through the Write Read STATUS Register (RDSR) command will be exe- Enable (WREN) instruction as shown in
Section 5.1
cuted by the device.
"Write Enable Instruction (WREN)"
and the Write Disable ( A logic ‘0’ bit in this position indicates the device is WRDI) instruction as shown in
Section 5.2 "Write Disable Instruction (WRDI)"
. These functions ready to accept new SRAM Read/Write commands. change the status of the WEL bit (bit 1) in the STATUS register.
6.4 Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction
6.3 Ready/Busy Status Latch
provides access to the contents of the STATUS The Ready/Busy Status Latch is used to indicate register. The STATUS register is read by asserting the whether the device is currently active in a nonvolatile CS pin followed by sending in a 05h opcode. The write operation. This bit is read-only and automatically device wil return the 8-bit STATUS register value on updated by the device. This bit is provided in bit posi- the SO pin. tion ‘0’. The STATUS register can be continuously read for data by continuing to read beyond the first 8-bit value returned. The 48L640 wil update the STATUS register value upon the completion of every eight bits, thereby allowing new STATUS register values to be read without having to issue a new RDSR instruction.
FIGURE 6-1: RDSR WAVEFORM
CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK RDSR Opcode SI 0 0 0 0 0 1 0 1 STATUS Register High-Impedance SO D D D D D D D D 2018-2019 Microchip Technology Inc.
Preliminary
DS20006055B-page 14 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L640 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L640 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Product ID System Trademarks Worldwide Sales and Service
48L640 TABLE 6-2: BLOCK WRITE-PROTECT BITS STATUS Register Bits [3:2] Protected Address Range Level BP1 BP0 48L640
0 0 0 None 1 0 1 1800-1FFF 2 1 0 1000-1FFF 3 1 1 0000-1FFF
6.2 Write Enable Latch
A logic ‘1’ bit indicates that the device is currently busy performing an SRAM to EEPROM transfer or EEPROM Enabling and disabling writing to the STATUS register to SRAM restore operation. During this time, only the and the SRAM array is accomplished through the Write Read STATUS Register (RDSR) command will be exe- Enable (WREN) instruction as shown in
Section 5.1
cuted by the device.
"Write Enable Instruction (WREN)"
and the Write Disable ( A logic ‘0’ bit in this position indicates the device is WRDI) instruction as shown in
Section 5.2 "Write Disable Instruction (WRDI)"
. These functions ready to accept new SRAM Read/Write commands. change the status of the WEL bit (bit 1) in the STATUS register.
6.4 Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction
6.3 Ready/Busy Status Latch
provides access to the contents of the STATUS The Ready/Busy Status Latch is used to indicate register. The STATUS register is read by asserting the whether the device is currently active in a nonvolatile CS pin followed by sending in a 05h opcode. The write operation. This bit is read-only and automatically device wil return the 8-bit STATUS register value on updated by the device. This bit is provided in bit posi- the SO pin. tion ‘0’. The STATUS register can be continuously read for data by continuing to read beyond the first 8-bit value returned. The 48L640 wil update the STATUS register value upon the completion of every eight bits, thereby allowing new STATUS register values to be read without having to issue a new RDSR instruction.
FIGURE 6-1: RDSR WAVEFORM
CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK RDSR Opcode SI 0 0 0 0 0 1 0 1 STATUS Register High-Impedance SO D D D D D D D D 2018-2019 Microchip Technology Inc.
Preliminary
DS20006055B-page 14 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L640 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L640 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Product ID System Trademarks Worldwide Sales and Service