Datasheet ADP5076 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| Pages / Page | 23 / 5 — Data Sheet. ADP5076. ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL … |
| Revision | A |
| File Format / Size | PDF / 725 Kb |
| Document Language | English |
Data Sheet. ADP5076. ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE. Parameter Rating. Table 4. Thermal Resistance
Model Line for this Datasheet
Text Version of Document
Data Sheet ADP5076 ABSOLUTE MAXIMUM RATINGS Table 3. THERMAL RESISTANCE Parameter Rating
Thermal performance is directly linked to printed circuit board PVIN, AVIN −0.3 V to +6 V (PCB) design and operating environment. Careful attention to SW1 −0.3 V to +40 V PCB thermal design is required. SW2 PVIN − 40 V to PVIN + 0.3 V θJA is the natural convection junction-to-ambient thermal PGND, AGND −0.3 V to +0.3 V resistance measured in a one cubic foot sealed enclosure. θJC is EN1, EN2, FB1, FB2, SYNC −0.3 V to +6 V the junction-to-case thermal resistance. ΨJT is the junction-to- COMP1, COMP2, SLEW, SS, −0.3 V to AVIN + 0.3 V top of package thermal characterization parameter. SEQ, VREF Operating Junction −40°C to +125°C θJA and ΨJT are based on a 4-layer PCB (two signal and two Temperature Range power planes). θJC is measured at the top of the package and is Storage Temperature Range −65°C to +150°C independent of the PCB. The ΨJT value is more appropriate for Soldering Conditions JEDEC J-STD-020 calculating junction to case temperature in the application. Stresses at or above those listed under Absolute Maximum
Table 4. Thermal Resistance
Ratings may cause permanent damage to the product. This is a
Package Type θJA θJC ΨJT Unit
stress rating only; functional operation of the product at these CB-20-14 50 0.54 0.13 C/W or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may
ESD CAUTION
affect product reliability. Rev. A | Page 5 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PULSE WIDTH MODULATION (PWM) MODE PULSE SKIP MODULATION MODE UVLO OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN STARTUP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
Thermal performance is directly linked to printed circuit board PVIN, AVIN −0.3 V to +6 V (PCB) design and operating environment. Careful attention to SW1 −0.3 V to +40 V PCB thermal design is required. SW2 PVIN − 40 V to PVIN + 0.3 V θJA is the natural convection junction-to-ambient thermal PGND, AGND −0.3 V to +0.3 V resistance measured in a one cubic foot sealed enclosure. θJC is EN1, EN2, FB1, FB2, SYNC −0.3 V to +6 V the junction-to-case thermal resistance. ΨJT is the junction-to- COMP1, COMP2, SLEW, SS, −0.3 V to AVIN + 0.3 V top of package thermal characterization parameter. SEQ, VREF Operating Junction −40°C to +125°C θJA and ΨJT are based on a 4-layer PCB (two signal and two Temperature Range power planes). θJC is measured at the top of the package and is Storage Temperature Range −65°C to +150°C independent of the PCB. The ΨJT value is more appropriate for Soldering Conditions JEDEC J-STD-020 calculating junction to case temperature in the application. Stresses at or above those listed under Absolute Maximum
Table 4. Thermal Resistance
Ratings may cause permanent damage to the product. This is a
Package Type θJA θJC ΨJT Unit
stress rating only; functional operation of the product at these CB-20-14 50 0.54 0.13 C/W or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may
ESD CAUTION
affect product reliability. Rev. A | Page 5 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PULSE WIDTH MODULATION (PWM) MODE PULSE SKIP MODULATION MODE UVLO OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN STARTUP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
