Datasheet CMX655D (CML Microcircuits) - 41

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7 6 5 4 3 2 1 0
0 0 SAI LOUT PAMP 0 MICL MICR
SAI Serial Audio Interface
0 Serial Audio Interface disabled. 1 Serial Audio Interface enabled.
LOUT Lineout
0 Lineout disabled. 1 Lineout enabled.
PAMP Power Amplifier
0 Power amplifier disabled. 1 Power amplifier enabled. PAMP is automatically cleared to 0 if the
ISR
AMPOC or THERM bits are set to 1.
MICL Microphone Left Channel
0 Microphone left channel disabled. 1 Microphone left channel enabled.
MICR Microphone Right Channel
0 Microphone right channel disabled. 1 Microphone right channel enabled.
COMMAND ($33)
Command Register (W) Reset Value: $00
7 6 5 4 3 2 1 0
CMD
CMD Command
$00 Clock Stop. $01 Clock Start. $02-$FE Reserved. $FF Soft Reset (sets all registers back to their reset value). This register will always be read back as 0.
5.11 Register Address Map
All device registers are byte addressable. Programmable fields that occupy consecutive byte address locations will be updated with the new written value following a write to the least-significant address byte of the field which resides in the upper address location. Registers which require the main clock to be active are indicated by Yes in the Main Clock column of Table 9 and accesses to these registers should not be attempted if the main clock is inactive.
Table 9 Register Address Map Address Register Description Reset R/W Main Clock Interrupt and Status
$00
ISR
Interrupt Status Register $00 R No $01
ISM
Interrupt Status Mask $00 R/W No $02
ISE
Interrupt Status Enable $00 R/W Yes
Clock & PLL
$03 CLKCTRL Clock Control $00 R/W No $04
RDIVHI
R-Divider High Byte $00 R/W No $05 RDIVLO R-Divider Low Byte $00 R/W No $06 NDIVHI N-Divider High Byte $00 R/W No $07 NDIVLO N-Divider Low Byte $00 R/W No $08 PLLCTRL PLL Control $00 R/W No  2019 CML Microsystems Plc 41 D/655/4 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655D 3 Pin List 3.1 CMX655D 4 External Components 4.1 CMX655D 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Noise Gate 5.6.2.1 Noise Gate Registers 5.6.3 Record Level Detection 5.6.3.1 Record Level Detection Registers 5.6.4 Playback Preamplifier Gain 5.6.4.1 Playback Preamplifier Gain Register 5.6.5 Playback Volume Control 5.6.5.1 Playback Volume Register 5.6.6 Automatic Level Control 5.6.6.1 ALC Registers 5.6.7 Digital Sidetone 5.6.7.1 Digital Sidetone Register 5.6.8 Voice Filters 5.6.8.1 Low Pass Filter 5.6.8.2 DC Blocking Filter 5.6.8.3 High Pass Filter 5.6.8.4 Voice Filters Registers 5.6.9 Channel Multiplexing 5.6.10 Click-and-Pop Reduction 5.6.10.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 Configuration 6.1.3 Enable Audio Channels 6.1.4 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D End of Document cmlmicro.com CMX655D - Ultra-low Power Voice Codec - CML Micro