2 ADC/8 DAC with PLL,192 kHz, 24-Bit CodecData SheetADAU1328FEATURESGENERAL DESCRIPTIONPLL generated or direct master clock The ADAU1328 is a high performance, single-chip codec that Low EMI design provides two analog-to-digital converters (ADCs) with differential 108 dB DAC/107 dB ADC dynamic range and SNR input and eight digital-to-analog converters (DACs) with −94 dB THD + N single-ended output using the Analog Devices, Inc. patented Single 3.3 V supply multibit sigma-delta (Σ-Δ) architecture. An SPI port is included, Tolerance for 5 V logic inputs allowing a microcontrol er to adjust volume and many other Supports 24 bits and 8 kHz to 192 kHz sample rates parameters. The ADAU1328 operates from 3.3 V digital and Differential ADC input analog supplies. The ADAU1328 is available in a 48-lead Single-ended DAC output (single-ended output) LQFP. Other members of this family Log volume control with autoramp function include a differential DAC output version. SPI® controllable for flexibility Software controllable clickless mute The ADAU1328 is designed for low EMI. This consideration is Software power-down apparent in both the system and circuit design architectures. Right justified, left justified, I2S and TDM modes By using the on-board PLL to derive the master clock from the Master and slave modes up to 16-channel in/out LR clock or from an external crystal, the ADAU1328 eliminates 48-lead LQFP the need for a separate high frequency master clock and can