Datasheet LT8614 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 42V, 4A Synchronous Step-Down Silent Switcher with 2.5μA Quiescent Current |
| Pages / Page | 24 / 10 — PIN FUNCTIONS SYNC/MODE (Pin 17):. FB (Pin 20):. SW (Exposed Pad Pins 21, … |
| Revision | E |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
PIN FUNCTIONS SYNC/MODE (Pin 17):. FB (Pin 20):. SW (Exposed Pad Pins 21, 22):. GND (Pins 18):. PG (Pin 19):. BLOCK DIAGRAM
Text Version of Document
LT8614
PIN FUNCTIONS SYNC/MODE (Pin 17):
External Clock Synchronization
FB (Pin 20):
The LT8614 regulates the FB pin to 0.970V. Input. Ground this pin for low ripple Burst Mode operation Connect the feedback resistor divider tap to this pin. Also, at low output loads. Tie to a clock source for synchroniza- connect a phase lead capacitor between FB and VOUT. tion to an external frequency. Apply a DC voltage of 3V or Typically, this capacitor is 4.7pF to 22pF. higher or tie to INTVCC for pulse-skipping mode. When
SW (Exposed Pad Pins 21, 22):
The exposed pads should in pulse-skipping mode, the IQ will increase to several to connected and soldered to the SW trace for good ther- hundred µA. Do not float this pin. mal performance. If necessary due to manufacturing limi-
GND (Pins 18):
LT8614 Ground Pin. Connect this pin to tations Pins 21 and 22 may be left disconnected, however system ground and to the ground plane. thermal performance will be degraded.
PG (Pin 19):
The PG pin is the open-drain output of an internal comparator. PG remains low until the FB pin is within ±9% of the final regulation voltage, and there are no fault conditions. PG is valid when VIN is above 3.4V, regardless of EN/UV pin state.
BLOCK DIAGRAM
VIN2 V 13 IN1 VIN 4 CIN2 CIN3 CIN1 – INTERNAL 0.97V REF + 3.4V BIAS R3 1V + REG 1 OPT EN/UV 14 – SHDN SLOPE COMP INTV R4 CC 2 OPT C OSCILLATOR VCC ERROR PG 200kHz TO 3MHz BST 19 ±9% AMP 3 + V C + C BURST SWITCH M1 BST V – DETECT LOGIC SW L OUT AND VOUT ANTI- 8, 9, 21, 22 COUT SHOOT SHDN C1 R1 TSD THROUGH M2 INTVCC UVLO R2 VIN UVLO FB GND1 20 SHDN CSS 6, 7 TSD OPT 2.2µA VIN UVLO TR/SS GND2 16 10, 11 RT RT 15 SYNC/MODE 17 GND 8614 BD 18 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Applications Related Parts
PIN FUNCTIONS SYNC/MODE (Pin 17):
External Clock Synchronization
FB (Pin 20):
The LT8614 regulates the FB pin to 0.970V. Input. Ground this pin for low ripple Burst Mode operation Connect the feedback resistor divider tap to this pin. Also, at low output loads. Tie to a clock source for synchroniza- connect a phase lead capacitor between FB and VOUT. tion to an external frequency. Apply a DC voltage of 3V or Typically, this capacitor is 4.7pF to 22pF. higher or tie to INTVCC for pulse-skipping mode. When
SW (Exposed Pad Pins 21, 22):
The exposed pads should in pulse-skipping mode, the IQ will increase to several to connected and soldered to the SW trace for good ther- hundred µA. Do not float this pin. mal performance. If necessary due to manufacturing limi-
GND (Pins 18):
LT8614 Ground Pin. Connect this pin to tations Pins 21 and 22 may be left disconnected, however system ground and to the ground plane. thermal performance will be degraded.
PG (Pin 19):
The PG pin is the open-drain output of an internal comparator. PG remains low until the FB pin is within ±9% of the final regulation voltage, and there are no fault conditions. PG is valid when VIN is above 3.4V, regardless of EN/UV pin state.
BLOCK DIAGRAM
VIN2 V 13 IN1 VIN 4 CIN2 CIN3 CIN1 – INTERNAL 0.97V REF + 3.4V BIAS R3 1V + REG 1 OPT EN/UV 14 – SHDN SLOPE COMP INTV R4 CC 2 OPT C OSCILLATOR VCC ERROR PG 200kHz TO 3MHz BST 19 ±9% AMP 3 + V C + C BURST SWITCH M1 BST V – DETECT LOGIC SW L OUT AND VOUT ANTI- 8, 9, 21, 22 COUT SHOOT SHDN C1 R1 TSD THROUGH M2 INTVCC UVLO R2 VIN UVLO FB GND1 20 SHDN CSS 6, 7 TSD OPT 2.2µA VIN UVLO TR/SS GND2 16 10, 11 RT RT 15 SYNC/MODE 17 GND 8614 BD 18 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Typical Applications Related Parts
