Preliminary Datasheet EPC2152 (Efficient Power Conversion) - 9

EPC2152 – 80 V, 12.5 A ePower™ Stage PRELIMINARY Application Information
Layout Guidelines loop inductance results in lower voltage overshoot, increased input voltage Monolithic integration of the half-bridge capability, and reduced EMI. output FETs as well as their associated gate drivers significantly reduce parasitic A recommended layout technique for the common source inductance (CSI) and gate EPC2152 device is shown in Figure 5a [2]. drive loop inductance. What remains is the This PCB layout uses the concept of creating high frequency power loop inductance that a low-profile magnetic field cancel ation is controlled by the PCB layout of the DC loop in a multilayer PCB as shown in Figure input capacitors in relationship to the 5b. The design utilizes the first inner layer current flow direction through the pin connected to the GND plane as a power loop configuration and layout geometry of the return path. Separated only by a thin output FETs in the half-bridge power stage. substrate, the top layer power loop and first Experimental data confirmed that the inner layer current return path directly efficiency curves can be impacted by as underneath generate opposing magnetic much as 4% depending on the power loop fields with induced currents that have inductance varying from 0.4 nH to 3 nH [1]. opposite direction. The result is a Another negative effect of excessive power cancellation of magnetic fields that loop inductance is the over-voltage spike at translates into a reduction in parasitic the SW node. Decreasing the high frequency inductance.
Figure 5a: Top View Figure 5b: Side View Figure 5: Recommended layout technique to minimize power loop inductance
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