Datasheet ADAR1000 (Analog Devices) - 61
| Manufacturer | Analog Devices |
| Description | 8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer |
| Pages / Page | 65 / 61 — Data Sheet. ADAR1000. Address: 0x044, Reset: 0x00, Name: TX_CH4_MEM. [ 7 … |
| Revision | A |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
Data Sheet. ADAR1000. Address: 0x044, Reset: 0x00, Name: TX_CH4_MEM. [ 7 ] T X _CH 4 _RAM _FET CH ( R/W )
Model Line for this Datasheet
Text Version of Document
Data Sheet ADAR1000 Address: 0x044, Reset: 0x00, Name: TX_CH4_MEM
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 ] T X _CH 4 _RAM _FET CH ( R/W ) [ 6 :0 ] T X _CH 4 _RAM _IN D EX ( R/W )
Ge t Trans m it Channe l 4 Be am Se tting s RAM Ind e x fo r Trans m it Channe l 4 fro m RAM
Table 85. Bit Descriptions for TX_CH4_MEM Bit(s) Bit Name Settings Description Reset Access
7 TX_CH4_RAM_FETCH Get Transmit Channel 4 Beam Settings from RAM 0x0 R/W [6:0] TX_CH4_RAM_INDEX RAM Index for Transmit Channel 4 0x0 R/W
Address: 0x045, Reset: 0x00, Name: REV_ID
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] REV _I D ( R)
Chip Rev ision ID
Table 86. Bit Descriptions for REV_ID Bit(s) Bit Name Settings Description Reset Access
[7:0] REV_ID Chip Revision ID 0x0 R
Address: 0x046, Reset: 0x00, Name: CH1_PA_BIAS_OFF
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] EX T_PA1 _BI AS_OFF ( R/W )
Ex t ernal Bias for Ex t ernal PA 1
Table 87. Bit Descriptions for CH1_PA_BIAS_OFF Bit(s) Bit Name Settings Description Reset Access
[7:0] EXT_PA1_BIAS_OFF External Bias for External PA 1 0x0 R/W
Address: 0x047, Reset: 0x00, Name: CH2_PA_BIAS_OFF
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] EX T_PA2 _BI AS_OFF ( R/W )
Ex t ernal Bias for Ex t ernal PA 2
Table 88. Bit Descriptions for CH2_PA_BIAS_OFF Bit(s) Bit Name Settings Description Reset Access
[7:0] EXT_PA2_BIAS_OFF External Bias for External PA 2 0x0 R/W
Address: 0x048, Reset: 0x00, Name: CH3_PA_BIAS_OFF
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] EX T_PA3 _BI AS_OFF ( R/W )
Ex t ernal Bias for Ex t ernal PA 3
Table 89. Bit Descriptions for CH3_PA_BIAS_OFF Bit(s) Bit Name Settings Description Reset Access
[7:0] EXT_PA3_BIAS_OFF External Bias for External PA 3 0x0 R/W Rev. A | Page 61 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 ] T X _CH 4 _RAM _FET CH ( R/W ) [ 6 :0 ] T X _CH 4 _RAM _IN D EX ( R/W )
Ge t Trans m it Channe l 4 Be am Se tting s RAM Ind e x fo r Trans m it Channe l 4 fro m RAM
Table 85. Bit Descriptions for TX_CH4_MEM Bit(s) Bit Name Settings Description Reset Access
7 TX_CH4_RAM_FETCH Get Transmit Channel 4 Beam Settings from RAM 0x0 R/W [6:0] TX_CH4_RAM_INDEX RAM Index for Transmit Channel 4 0x0 R/W
Address: 0x045, Reset: 0x00, Name: REV_ID
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] REV _I D ( R)
Chip Rev ision ID
Table 86. Bit Descriptions for REV_ID Bit(s) Bit Name Settings Description Reset Access
[7:0] REV_ID Chip Revision ID 0x0 R
Address: 0x046, Reset: 0x00, Name: CH1_PA_BIAS_OFF
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] EX T_PA1 _BI AS_OFF ( R/W )
Ex t ernal Bias for Ex t ernal PA 1
Table 87. Bit Descriptions for CH1_PA_BIAS_OFF Bit(s) Bit Name Settings Description Reset Access
[7:0] EXT_PA1_BIAS_OFF External Bias for External PA 1 0x0 R/W
Address: 0x047, Reset: 0x00, Name: CH2_PA_BIAS_OFF
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] EX T_PA2 _BI AS_OFF ( R/W )
Ex t ernal Bias for Ex t ernal PA 2
Table 88. Bit Descriptions for CH2_PA_BIAS_OFF Bit(s) Bit Name Settings Description Reset Access
[7:0] EXT_PA2_BIAS_OFF External Bias for External PA 2 0x0 R/W
Address: 0x048, Reset: 0x00, Name: CH3_PA_BIAS_OFF
7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0
[ 7 :0 ] EX T_PA3 _BI AS_OFF ( R/W )
Ex t ernal Bias for Ex t ernal PA 3
Table 89. Bit Descriptions for CH3_PA_BIAS_OFF Bit(s) Bit Name Settings Description Reset Access
[7:0] EXT_PA3_BIAS_OFF External Bias for External PA 3 0x0 R/W Rev. A | Page 61 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide