Datasheet KSZ8862-16M, KSZ8862-32M (Microchip) - 31

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KSZ8862-16M/-32M FIGURE 3-7: KSZ8862M 8-BIT, 16-BIT, AND 32-BIT DATA BUS CONNECTIONS
KSZ8862-16 KSZ8862-16 KSZ8862-32 HA[1] A[1] HA[1] A[1] GND A[1] HA[15:2] A[15:2] HA[15:2] A[15:2] HA[15:2] A[15:2] HD[7:0] D[7:0] HD[7:0] D[7:0] HD[7:0] D[7:0] HD[15:8] D[15:8] HD[15:8] D[15:8] D[15:8] HD[23:16] D[23:16] HD[31:24] D[31:24] HA[0] BE0N HA[0] BE0N nHBE[0] BE0N VDD BE1N nSBHE BE1N nHBE[1] BE1N nHBE[2] BE2N nHBE[3] BE3N 16-bit Data Bus 32-bit Data Bus 8-bit Data Bus (for example: ISA-like) (for example: EISA-like) 3.3.3 BIU IMPLEMENTATION PRINCIPLES Because KSZ8862M is an I/O device with 16 addressable locations, address decoding is based on the values of A15- A4 and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is assumed (BE3N – BE0N are ignored). If address latching is required, the address is latched on the rising edge of ADSN and is transparent when ADSN = 0. • Byte, word, and double word data buses and accesses (transfers) are supported. • Internal byte swapping is not implemented and word swapping is supported internally. Refer to Figure 3-7 for the appropriate 8-bit, 16-bit, and 32-bit data bus connection. • Because independent sets of synchronous and asynchronous signals are provided, synchronous and asynchro- nous cycles can be mixed or interleaved as long as they are not active simultaneously. • The asynchronous interface uses RDN and WRN signal strobes for data latching. If necessary, ARDY is de- asserted on the leading edge of the strobe. • The VLBUS-like synchronous interface uses BCLK, ADSN, and SWR and CYCLEN to control read and write operations and generate SRDYN to insert the wait state, if necessary, when VLBUSN = 0. For read, the data must be held until RDYRTNN is asserted. The EISA-like burst transfer is supported using synchronous interface signals and DATACSN when I/O signal VLBUSN = 1. Both the system/host/memory and KSZ8862M are capable of inserting wait states. To set the system/host/memory to insert a wait state, assert RDYRTNN signal. To set the KSZ8862M to insert a wait state, assert SRDYN signal.
3.4 Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each queue contains 4 KB of memory for back-to-back, non-blocking frame transfer performance. It provides a group of control registers for system control, frame status registers for current packet transmit/receive status, and interrupts to inform the host of the real time TX/RX status. 3.4.1 TRANSMIT QUEUE (TXQ) FRAME FORMAT The frame format for the transmit queue is shown in Table 3-3. The first word contains the control information for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon whether hardware CRC checksum generation is enabled.  2020 Microchip Technology Inc.

DS00003324A-page 31 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 Auto-Negotiation Timing 7.10 Reset Timing 7.11 EEPROM Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service