Datasheet KSZ8993M (Microchip) - 6
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 74 / 6 — KSZ8993M. TABLE 2-1:. SIGNALS. Pin. Pin Name. Type. Description. Number. … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
KSZ8993M. TABLE 2-1:. SIGNALS. Pin. Pin Name. Type. Description. Number. [LEDSEL1, LEDSEL0] [0, 0]. [0, 1]. [LEDSEL1, LEDSEL0]. [1, 0]. [1, 1]
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KSZ8993M TABLE 2-1: SIGNALS Pin Pin Name Type Description Number
Port 1 LED Indicators
[LEDSEL1, LEDSEL0] [0, 0] [0, 1]
P1LED3 — — P1LED2 Link/Activity 100Link/Activity P1LED1 Full-Duplex/Col 10Link/Activity P1LED0 Speed Full-Duplex 1 P1LED2 2 P1LED1 IPU/O
[LEDSEL1, LEDSEL0]
3 P1LED0
[1, 0] [1, 1]
P1LED3 Activity — P1LED2 Link — P1LED1 Full-Duplex/Col — P1LED0 Speed —
Note:
LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P1LED3 is pin 25. During reset, P1LED[2:0] are inputs for internal testing. Port 2 LED Indicators
[LEDSEL1, LEDSEL0] [0, 0] [0, 1]
P2LED3 — — P2LED2 Link/Activity 100Link/Activity P2LED1 Full-Duplex/Col 10Link/Activity P2LED0 Speed Full-Duplex 4 P2LED2 5 P2LED1 IPU/O
[LEDSEL1, LEDSEL0]
6 P2LED0
[1, 0] [1, 1]
P2LED3 Activity — P2LED2 Link — P2LED1 Full-Duplex/Col — P2LED0 Speed —
Note:
LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P2LED3 is pin 20. During reset, P2LED[2:0] are inputs for internal testing 7 DGND GND Digital ground. 8 VDDIO P 3.3V digital VDD 9 NC IPD No connect 10 NC IPD No connect 11 NC IPU No connect 1 = Advertise the switch’s flow control capability via auto negotiation. 12 ADVFC IPU 0 = Will not advertise the switch’s flow control capability via auto negoti- ation. DS00003066A-page 6
2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Port 1 LED Indicators
[LEDSEL1, LEDSEL0] [0, 0] [0, 1]
P1LED3 — — P1LED2 Link/Activity 100Link/Activity P1LED1 Full-Duplex/Col 10Link/Activity P1LED0 Speed Full-Duplex 1 P1LED2 2 P1LED1 IPU/O
[LEDSEL1, LEDSEL0]
3 P1LED0
[1, 0] [1, 1]
P1LED3 Activity — P1LED2 Link — P1LED1 Full-Duplex/Col — P1LED0 Speed —
Note:
LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P1LED3 is pin 25. During reset, P1LED[2:0] are inputs for internal testing. Port 2 LED Indicators
[LEDSEL1, LEDSEL0] [0, 0] [0, 1]
P2LED3 — — P2LED2 Link/Activity 100Link/Activity P2LED1 Full-Duplex/Col 10Link/Activity P2LED0 Speed Full-Duplex 4 P2LED2 5 P2LED1 IPU/O
[LEDSEL1, LEDSEL0]
6 P2LED0
[1, 0] [1, 1]
P2LED3 Activity — P2LED2 Link — P2LED1 Full-Duplex/Col — P2LED0 Speed —
Note:
LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P2LED3 is pin 20. During reset, P2LED[2:0] are inputs for internal testing 7 DGND GND Digital ground. 8 VDDIO P 3.3V digital VDD 9 NC IPD No connect 10 NC IPD No connect 11 NC IPU No connect 1 = Advertise the switch’s flow control capability via auto negotiation. 12 ADVFC IPU 0 = Will not advertise the switch’s flow control capability via auto negoti- ation. DS00003066A-page 6
2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
