Datasheet KSZ8993M (Microchip) - 9
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 74 / 9 — KSZ8993M. TABLE 2-1:. SIGNALS (CONTINUED). Pin. Pin Name. Type. … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
KSZ8993M. TABLE 2-1:. SIGNALS (CONTINUED). Pin. Pin Name. Type. Description. Number
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KSZ8993M TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Name Type Description Number
Half-duplex back pressure 68 BPEN IPD 1 = Enable 0 = Disable Special MAC mode In this mode, the switch will do faster back-offs than normal. 69 SMAC IPD 1 = Enable 0 = Disable LED display mode select 70 LEDSEL0 IPD See description for pins 1 and 4. 71 SMTXEN IPD Switch MII transmit enable 72 SMTXD3 IPD Switch MII transmit data bit 3 73 SMTXD2 IPD Switch MII transmit data bit 2 74 SMTXD1 IPD Switch MII transmit data bit 1 75 SMTXD0 IPD Switch MII transmit data bit 0 76 SMTXER IPD Switch MII transmit error Switch MII transmit clock 77 SMTXC IPD/O Output in PHY MII mode Input in MAC MII mode 78 DGND GND Digital ground 79 VDDIO P 3.3V digital VDD Switch MII receive clock. 80 SMRXC IPD/O Output in PHY MII mode Input in MAC MII mode 81 SMRXDV O Switch MII receive data valid Switch MII receive data bit 3 Strap option: Switch MII full-duplex flow control 82 SMRXD3 IPD/O PD (default) = Disable PU = Enable Switch MII receive bit 2 Strap option: Switch MII is in 83 SMRXD2 IPD/O PD (default) = Full-duplex mode PU = Half-duplex mode Switch MII receive bit 1 Strap option: Switch MII is in 84 SMRXD1 IPD/O PD (default) = 100 Mbps mode PU = 10 Mbps mode Switch MII receive bit 0 Strap option: Switch will accept packet size up to 85 SMRXD0 IPD/O PD (default) = 1536 bytes (inclusive) PU = 1522 bytes (tagged), 1518 bytes (untagged) 86 SCOL IPD/O Switch MII collision detect 87 SCRS IPD/O Switch MII carrier sense 2019 Microchip Technology Inc.
DS00003066A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Half-duplex back pressure 68 BPEN IPD 1 = Enable 0 = Disable Special MAC mode In this mode, the switch will do faster back-offs than normal. 69 SMAC IPD 1 = Enable 0 = Disable LED display mode select 70 LEDSEL0 IPD See description for pins 1 and 4. 71 SMTXEN IPD Switch MII transmit enable 72 SMTXD3 IPD Switch MII transmit data bit 3 73 SMTXD2 IPD Switch MII transmit data bit 2 74 SMTXD1 IPD Switch MII transmit data bit 1 75 SMTXD0 IPD Switch MII transmit data bit 0 76 SMTXER IPD Switch MII transmit error Switch MII transmit clock 77 SMTXC IPD/O Output in PHY MII mode Input in MAC MII mode 78 DGND GND Digital ground 79 VDDIO P 3.3V digital VDD Switch MII receive clock. 80 SMRXC IPD/O Output in PHY MII mode Input in MAC MII mode 81 SMRXDV O Switch MII receive data valid Switch MII receive data bit 3 Strap option: Switch MII full-duplex flow control 82 SMRXD3 IPD/O PD (default) = Disable PU = Enable Switch MII receive bit 2 Strap option: Switch MII is in 83 SMRXD2 IPD/O PD (default) = Full-duplex mode PU = Half-duplex mode Switch MII receive bit 1 Strap option: Switch MII is in 84 SMRXD1 IPD/O PD (default) = 100 Mbps mode PU = 10 Mbps mode Switch MII receive bit 0 Strap option: Switch will accept packet size up to 85 SMRXD0 IPD/O PD (default) = 1536 bytes (inclusive) PU = 1522 bytes (tagged), 1518 bytes (untagged) 86 SCOL IPD/O Switch MII collision detect 87 SCRS IPD/O Switch MII carrier sense 2019 Microchip Technology Inc.
DS00003066A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
