Datasheet VSC7420-02, VSC7421-02, VSC7422-02 (Microchip) - 616

Package Information
Figure 79 • Package Drawing TQFP
Top View Bottom View 24.00 5 6 Pin 1 Pin 1 corner 22.00 corner 26.00 4 12.50 D 11.40 ±0.10 3 Detail B 224 224 1 1 13 (13×) A78 3 3 A1 4 8.40 ±0.10 A B 26.00 24.00 22.00 9.50 8.00 5 6 0.22 ±0.05 (78×) Detail D Detail C 10.50 0.20 (4×) C A-B D Ø 0.05 M H A-B D 0.20 (4×) H A-B D Detail E Side View Detail A Detail A 0.05 0.05 0.20 min 11°–13° 0° min H 2 2 H 0.10 C 1.20 1.00 0.08/0.20 R ±0.05 C 0.08 max C 0.25 0°–7° Ø 0.08 M C A-B D C Seating plane 9 0.08 R min C +0.049 Gauge plane 0.051–0.051 0.60 ±0.15 Detail B Detail C 3 1.00 0.40 BSC Detail D Ø 0.05 M Even land side 6.85/5.35 H A- 0.40 ±0.10 B D (4×) A, B, or D 0.18 Ø 0.10 M H A-B D ±0.05 0.40 maximum cut width Detail E 3 8 0.25 maximum cut depth 0.50 BSC Odd land side
Notes
1. All dimensions and tolerances are in millimeters (mm). 2. Datum plane H is located at the mold parting line and coincident lead, where the 0.50 BSC D lead exits the plastic body at the bottom of the parting line. 3. Datums A–B and D are determined at the centerline, between leads, where the D leads exit the plastic body at datum plane H. 4. Determined at seating plane C. Cross section C-C 5. Dimensions do not include a mold protrusion allowance of 0.254 mm. 8 Ø 0.08 M C A-B D 6. Determined at datum plane H. 7. Top of package may be smaller than the bottom of package by 0.15 mm. 0.18 ±0.05 Cross section D-D 8. Dimension does not include a dambar protrusion allowance of 0.08 mm total in 14 Base metal excess of the pin width maximum. 0.144/0.200 with lead 0.08 H 0.22 ±0.05 9. Measured from the seating plane to the lowest point of the package body. finish 0 ±0.05 10. Exposed pad size tolerance is 0.10 mm maximum. 11. Exposed pad is coplanar with the bottom of the package within 0.05 mm. Base metal with lead 0.152 12. Unilateral coplanarity zone applies to the exposed pad and terminals. finish 13. Mechanical connect tabs are counted as ground signal pins and are included in the total package pin count. Mold compound 14. Applies to the flat section of the lead between 0.10 mm and 0.25 mm from lead tip. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 586 Document Outline 1 Revision History 1.1 Revision 4.3 1.2 Revision 4.2 1.3 Revision 4.1 1.4 Revision 4.0 1.5 Revision 2.0 2 Introduction 2.1 Register Notation 2.2 Standard References 2.3 Terms and Abbreviations 3 Product Overview 3.1 General Features 3.1.1 Layer-2 Switching 3.1.2 Multicast 3.1.3 Quality of Service 3.1.4 Security 3.1.5 Management 3.2 Applications 3.3 Related Products 3.4 Functional Overview 3.4.1 Frame Arrival 3.4.2 Frame Classification 3.4.3 Policing 3.4.4 Layer-2 Forwarding 3.4.5 Shared Queue System and Egress Scheduler 3.4.6 Rewriter and Frame Departure 3.4.7 CPU Port Module 3.4.8 CPU System and Interfaces 4 Functional Descriptions 4.1 Port Modules 4.1.1 Port Module Numbering and Macro Connections 4.1.2 MAC 4.1.3 PCS 4.2 SERDES6G 4.2.1 SERDES6G Basic Configuration 4.2.2 SERDES6G Loopback Modes 4.2.3 SERDES6G Deserializer Configuration 4.2.4 SERDES6G Serializer Configuration 4.2.5 SERDES6G Input Buffer Configuration 4.2.6 SERDES6G Output Buffer Configuration 4.2.7 SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX 4.2.8 SERDES6G Energy Efficient Ethernet 4.2.9 SERDES6G Data Inversion 4.2.10 SERDES6G Signal Detection Enhancements 4.2.11 SERDES6G High-Speed I/O Configuration Bus 4.3 Copper Transceivers 4.3.1 Register Access 4.3.2 Cat5 Twisted Pair Media Interface 4.3.3 LED Interface 4.3.4 Ethernet Inline Powered Devices 4.3.5 IEEE 802.3af PoE Support 4.3.6 ActiPHY™ Power Management 4.3.7 Testing Features 4.3.8 VeriPHY™ Cable Diagnostics 4.4 Statistics 4.5 Classifier 4.5.1 General Data Extraction Setup 4.5.2 Frame Acceptance Filtering 4.5.3 QoS and DSCP Classification 4.5.4 VLAN Classification 4.5.5 Link Aggregation Code Generation 4.5.6 CPU Forwarding Determination 4.6 Analyzer 4.6.1 MAC Table 4.6.2 VLAN Table 4.6.3 Forwarding Engine 4.6.4 Analyzer Monitoring 4.7 Policers and Ingress Shapers 4.7.1 Policers 4.7.2 Ingress Shapers 4.8 Shared Queue System 4.8.1 Buffer Management 4.8.2 Frame Reference Management 4.8.3 Resource Depletion Condition 4.8.4 Configuration Example 4.8.5 Watermark Programming and Consumption Monitoring 4.8.6 Advanced Resource Management 4.8.7 Ingress Pause Request Generation 4.8.8 Tail Dropping 4.8.9 Test Utilities 4.8.10 Energy Efficient Ethernet 4.9 Scheduler and Shaper 4.9.1 Egress Shapers 4.9.2 Deficit Weighted Round Robin 4.9.3 Shaping and DWRR Scheduling Examples 4.10 Rewriter 4.10.1 VLAN Editing 4.10.2 DSCP Remarking 4.10.3 FCS Updating 4.10.4 CPU Extraction Header Insertion 4.11 CPU Port Module 4.11.1 Frame Extraction 4.11.2 Frame Injection 4.11.3 Network Processor Interface (NPI) 4.12 Clocking and Reset 5 VCore-Ie System and CPU Interface 5.1 VCore-Ie Configurations 5.2 Clocking and Reset 5.2.1 Watchdog Timer 5.3 Shared Bus 5.3.1 Shared Bus Arbitration 5.3.2 SI Memory Region 5.3.3 Switch Core Registers Memory Region 5.3.4 VCore-Ie Registers Memory Region 5.4 VCore-Ie CPU 5.4.1 Starting the VCore-Ie CPU 5.4.2 Accessing the VCore-Ie Shared Bus 5.4.3 Paged Access to VCore-Ie Shared Bus 5.4.4 Software Debug and Development 5.5 Manual Frame Injection and Extraction 5.5.1 Manual Frame Extraction 5.5.2 Manual Frame Injection 5.5.3 Frame Interrupts 5.6 External CPU Support 5.6.1 Register Access and Multimaster Systems 5.6.2 Serial Interface in Slave Mode 5.6.3 MIIM Interface in Slave Mode 5.6.4 Access to the VCore-Ie Shared Bus 5.6.5 Mailbox and Semaphores 5.7 VCore-Ie System Peripherals 5.7.1 Timers 5.7.2 UART 5.7.3 Two-Wire Serial Interface 5.7.4 MII Management Controller 5.7.5 GPIO Controller 5.7.6 Serial GPIO Controller 5.7.7 FAN Controller 5.7.8 Interrupt Controller 6 Features 6.1 Port Mapping 6.1.1 VSC7420-02 Port Mapping 6.1.2 VSC7421-02 Port Mapping 6.1.3 VSC7422-02 Port Mapping 6.2 Switch Control 6.2.1 Switch Initialization 6.3 Port Module Control 6.3.1 MAC Configuration Port Mode Control 6.3.2 SerDes Configuration Port Mode Control 6.3.3 Port Reset Procedure 6.3.4 Port Counters 6.4 Layer-2 Switch 6.4.1 Basic Switching 6.4.2 Standard VLAN Operation 6.4.3 Provider Bridges and Q-in-Q Operation 6.4.4 Private VLANs 6.4.5 Asymmetric VLANs 6.4.6 Spanning Tree Protocol 6.4.7 IEEE 802.1X: Network Access Control 6.4.8 Link Aggregation 6.4.9 Simple Network Management Protocol (SNMP) 6.4.10 Mirroring 6.5 IGMP and MLD Snooping 6.5.1 IGMP and MLD Snooping Configuration 6.5.2 IP Multicast Forwarding Configuration 6.6 Quality of Service (QoS) 6.6.1 Basic QoS Configuration 6.6.2 IPv4 and IPv6 DSCP Remarking 6.7 CPU Extraction and Injection 6.7.1 Forwarding to CPU 6.7.2 Frame Extraction 6.7.3 Frame Injection 6.7.4 Frame Extraction and Injection Using An External CPU 6.8 Energy Efficient Ethernet 7 Registers 7.1 Targets and Base Addresses 7.2 DEVCPU_ORG 7.2.1 DEVCPU_ORG:ORG 7.3 SYS 7.3.1 SYS:SYSTEM 7.3.2 SYS:SCH 7.3.3 SYS:SCH_LB 7.3.4 SYS:RES_CTRL 7.3.5 SYS:PAUSE_CFG 7.3.6 SYS:MMGT 7.3.7 SYS:MISC 7.3.8 SYS:STAT 7.3.9 SYS:POL 7.3.10 SYS:POL_MISC 7.3.11 SYS:ISHP 7.4 ANA 7.4.1 ANA:ANA 7.4.2 ANA:ANA_TABLES 7.4.3 ANA:PORT 7.4.4 ANA:COMMON 7.5 REW 7.5.1 REW:PORT 7.5.2 REW:COMMON 7.6 DEVCPU_GCB 7.6.1 DEVCPU_GCB:CHIP_REGS 7.6.2 DEVCPU_GCB:SW_REGS 7.6.3 DEVCPU_GCB:VCORE_ACCESS 7.6.4 DEVCPU_GCB:GPIO 7.6.5 DEVCPU_GCB:DEVCPU_RST_REGS 7.6.6 DEVCPU_GCB:MIIM 7.6.7 DEVCPU_GCB:MIIM_READ_SCAN 7.6.8 DEVCPU_GCB:RAM_STAT 7.6.9 DEVCPU_GCB:MISC 7.6.10 DEVCPU_GCB:SIO_CTRL 7.6.11 DEVCPU_GCB:FAN_CFG 7.6.12 DEVCPU_GCB:FAN_STAT 7.6.13 DEVCPU_GCB:MEMITGR 7.7 DEVCPU_QS 7.7.1 DEVCPU_QS:XTR 7.7.2 DEVCPU_QS:INJ 7.8 HSIO 7.8.1 HSIO:PLL5G_STATUS 7.8.2 HSIO:RCOMP_STATUS 7.8.3 HSIO:SERDES6G_ANA_CFG 7.8.4 HSIO:SERDES6G_DIG_CFG 7.8.5 HSIO:MCB_SERDES6G_CFG 7.9 DEV_GMII 7.9.1 DEV_GMII:PORT_MODE 7.9.2 DEV_GMII:MAC_CFG_STATUS 7.10 DEV 7.10.1 DEV:PORT_MODE 7.10.2 DEV:MAC_CFG_STATUS 7.10.3 DEV:PCS1G_CFG_STATUS 7.10.4 DEV:PCS1G_TSTPAT_CFG_STATUS 7.10.5 DEV:PCS_FX100_CONFIGURATION 7.10.6 DEV:PCS_FX100_STATUS 7.11 ICPU_CFG 7.11.1 ICPU_CFG:CPU_SYSTEM_CTRL 7.11.2 ICPU_CFG:SPI_MST 7.11.3 ICPU_CFG:MPU8051 7.11.4 ICPU_CFG:INTR 7.11.5 ICPU_CFG:TIMERS 7.11.6 ICPU_CFG:TWI_DELAY 7.12 UART 7.12.1 UART:UART 7.13 TWI 7.13.1 TWI:TWI 7.14 PHY 7.14.1 PHY:PHY_STD 7.14.2 PHY:PHY_EXT1 7.14.3 PHY:PHY_EXT2 7.14.4 PHY:PHY_GP 7.14.5 PHY:PHY_EEE 8 Electrical Specifications 8.1 DC Characteristics 8.1.1 Internal Pull-Up or Pull-Down Resistors 8.1.2 Reference Clock 8.1.3 SGMII DC Definitions and Test Circuits 8.1.4 Enhanced SerDes Interface 8.1.5 MIIM, GPIO, SI, JTAG, and Miscellaneous Signals 8.2 AC Characteristics 8.2.1 Reference Clock 8.2.2 Reset Timing 8.2.3 Enhanced SerDes Interface 8.2.4 MII Management 8.2.5 Serial CPU Interface (SI) Master Mode 8.2.6 Serial CPU Interface (SI) for Slave Mode 8.2.7 JTAG Interface 8.2.8 Serial Inputs/Outputs 8.2.9 Two-Wire Serial Interface 8.3 Current and Power Consumption 8.3.1 Current Consumption 8.3.2 Power Consumption 8.3.3 Power Supply Sequencing 8.4 Operating Conditions 8.5 Stress Ratings 9 Pin Descriptions for VSC7420XJQ-02 9.1 Pin Diagram for VSC7420XJQ-02 9.2 Pins by Function for VSC7420XJQ-02 9.2.1 Analog Bias Signals 9.2.2 Clock Circuits 9.2.3 General-Purpose Inputs and Outputs 9.2.4 JTAG Interface 9.2.5 MII Management Interface 9.2.6 Miscellaneous Signals 9.2.7 Power Supplies and Ground 9.2.8 Serial CPU Interface 9.2.9 Enhanced SerDes Interface 9.2.10 Twisted Pair Interface 9.3 Pins by Number for VSC7420XJQ-02 9.4 Pins by Name for VSC7420XJQ-02 10 Pin Descriptions for VSC7420XJG-02 10.1 Pin Identifications 10.2 Pin Diagram for VSC7420XJG-02 10.3 Pins by Function for VSC7420XJG-02 11 Pin Descriptions for VSC7421XJQ-02 11.1 Pin Diagram for VSC7421XJQ-02 11.2 Pins by Function for VSC7421XJQ-02 11.2.1 Analog Bias Signals 11.2.2 Clock Circuits 11.2.3 General-Purpose Inputs and Outputs 11.2.4 JTAG Interface 11.2.5 MII Management Interface 11.2.6 Miscellaneous Signals 11.2.7 Power Supplies and Ground 11.2.8 Serial CPU Interface 11.2.9 Enhanced SerDes Interface 11.2.10 Twisted Pair Interface 11.3 Pins by Number for VSC7421XJQ-02 11.4 Pins by Name for VSC7421XJQ-02 12 Pin Descriptions for VSC7421XJG-02 12.1 Pin Identifications 12.2 Pin Diagram for VSC7421XJG-02 12.3 Pins by Function for VSC7421XJG-02 13 Pin Descriptions for VSC7422XJQ-02 13.1 Pin Diagram for VSC7422XJQ-02 13.2 Pins by Function for VSC7422XJQ-02 13.2.1 Analog Bias Signals 13.2.2 Clock Circuits 13.2.3 General-Purpose Inputs and Outputs 13.2.4 JTAG Interface 13.2.5 MII Management Interface 13.2.6 Miscellaneous Signals 13.2.7 Power Supplies and Ground 13.2.8 Serial CPU Interface 13.2.9 Enhanced SerDes Interface 13.2.10 Twisted Pair Interface 13.3 Pins by Number for VSC7422XJQ-02 13.4 Pins by Name for VSC7422XJQ-02 14 Pin Descriptions for VSC7422XJG-02 14.1 Pin Identifications 14.2 Pin Diagram for VSC7422XJG-02 14.3 Pins by Function for VSC7422XJG-02 15 Package Information 15.1 Package Drawing 15.2 Thermal Specifications 15.3 Moisture Sensitivity 16 Design Guidelines 16.1 Power Supplies 16.2 Power Supply Decoupling 16.3 Reference Clock 16.3.1 Single-Ended RefClk Input 16.4 Interfaces 16.4.1 General Recommendations 16.4.2 SGMII Interface 16.4.3 Serial Interface 16.4.4 Enhanced SerDes Interface 16.4.5 Two-Wire Serial Interface 17 Design Considerations 17.1 10BASE-T mode unable to re-establish link 17.2 Software script for link performance 17.3 10BASE-T signal amplitude 17.4 Clause 45 register 7.60 17.5 Clause 45 register 3.22 17.6 Clause 45 register 3.1 17.7 Clause 45 register address post-increment 18 Ordering Information