Datasheet VSC7511 (Microchip) - 321
| Manufacturer | Microchip |
| Description | 4 Port Unmanaged Industrial Ethernet Switch |
| Pages / Page | 324 / 321 — 10.3.5. Two-Wire Serial Interface. 10.3.6. DDR3 SDRAM Interface. Figure … |
| File Format / Size | PDF / 4.7 Mb |
| Document Language | English |
10.3.5. Two-Wire Serial Interface. 10.3.6. DDR3 SDRAM Interface. Figure 109 •. 16-Bit DDR3 SDRAM Point-to-Point Routing
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Design Guidelines During PCIe startup (VCORE_CFG = 1001), only low swing signaling with no de-emphasis is supported, regardless of the VDD_VS voltage. After startup, configure the PCIe interface as desired.
10.3.5 Two-Wire Serial Interface
The two-wire serial interface is capable of suppressing small amplitude glitches. The duration of the glitch which can be suppressed is set in register ICPU_CFG::TWI_SPIKE_FILTER_CFG. The default value of 0 will suppress a 4ns glitch. It is recommended that SPIKE_FILTER_CFG be set to 12, which will suppress a 52ns glitch.
10.3.6 DDR3 SDRAM Interface
The DDR3 SDRAM interface is designed to interface with 8-bit or 16-bit DDR SDRAM devices. The maximum amount of physical memory that can be addressed is one gigabyte. Possible combinations of memory modules are: • One 8-bit device, connect to CS0 byte lane 0. • Two 8-bit devices, connect to CS0 and both byte lanes. • Four 8-bit devices, connect to both chip-selects and both byte lanes. • One 16-bit device, connect to CS0 and both byte lanes. • Two 16-bit devices, connect to both chip-selects and both byte lanes. When using a single 8-bit device, the memory controller must be configured for 8-bit mode. All other configurations use 16-bit mode. All signals on this interface must be connected one-to-one with the corresponding signals on the DDR SDRAM device. When using only one 8-bit device, the DDR_UDQS, DDR_UDQSn, DDR_UDM, and DDR_DQ[15:8] signals must be left unconnected. When using DDR2 SDRAM devices that has only four banks, the DDR_BA[2] signal must be left unconnected. When using four 8-bit devices or two 16-bit devices, the CS1 memory modules must be placed in- between the VSC7511 device and the CS0 memory modules so that the DDR-DQS, DDR-DM, and DDR_DQ signals pass the CS1 devices first before reaching the CS0 devices. The placement of the VSC7511 interface signals is optimized for point-to-point routing directly to a single DDR3 16-bit SDRAM.
Figure 109 • 16-Bit DDR3 SDRAM Point-to-Point Routing
Data Lane Address DRAM Switch Clock Device Address Because reflections are absorbed by the devices, keep the physical distance of all the SDRAM interface signals as low as possible. Omit external discrete termination on the address, command, control, and clock lines. When routing the DDR interface, attention must be paid to the skew, primary concern is skew within the byte lane between the differential strobe and the single-ended signals. Skew recommendations for the DDR interface are listed in the following table.
Table 249 • Recommended Skew Budget Description Signal Maximum Skew
Skew within byte lane 0 DDR_LDQS/DDR_LDQSn 50 ps Skew within byte lane 1 DDR_UDQS/DDR_UDQSn 50 ps VMDS-10488 VSC7511 Datasheet Revision 4.2 306 Document Outline 1 Revision History 1.1 Revision 4.2 1.2 Revision 4.1 1.3 Revision 4.0 1.4 Revision 2.1 1.5 Revision 2.0 2 Product Overview 2.1 General Features 2.1.1 Layer 2 Switching 2.1.2 Layer 2 Multicast 2.1.3 Quality of Service 2.1.4 Security 2.1.5 Management 2.1.6 Product Parameters 2.2 Applications 2.3 Functional Overview 2.3.1 Frame Arrival 2.3.2 Basic and Advanced Frame Classification 2.3.3 Versatile Content Aware Processor (VCAP) 2.3.4 Policing 2.3.5 Layer-2 Forwarding 2.3.6 Shared Queue System and Egress Scheduler 2.3.7 Rewriter and Frame Departure 2.3.8 CPU Port Module 2.3.9 Synchronous Ethernet and Precision Time Protocol 2.3.10 CPU System and Interfaces 3 Functional Descriptions 3.1 Port Numbering and Mappings 3.1.1 Supported SerDes Interfaces 3.1.2 PCIe Mode 3.1.3 Logical Port Numbers 3.2 Port Modules 3.2.1 MAC 3.2.2 PCS 3.3 SERDES1G 3.3.1 SERDES1G Basic Configuration 3.3.2 SERDES1G Loopback Modes 3.3.3 Synchronous Ethernet 3.3.4 SERDES1G Deserializer Configuration 3.3.5 SERDES1G Serializer Configuration 3.3.6 SERDES1G Input Buffer Configuration 3.3.7 SERDES1G Output Buffer Configuration 3.3.8 SERDES1G Clock and Data Recovery (CDR) in 100BASE-FX 3.3.9 Energy Efficient Ethernet 3.3.10 SERDES1G Data Inversion 3.4 SERDES6G 3.4.1 SERDES6G Basic Configuration 3.4.2 SERDES6G Loopback Modes 3.4.3 Synchronous Ethernet 3.4.4 SERDES6G Deserializer Configuration 3.4.5 SERDES6G Serializer Configuration 3.4.6 SERDES6G Input Buffer Configuration 3.4.7 SERDES6G Output Buffer Configuration 3.4.8 SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX 3.4.9 Energy Efficient Ethernet 3.4.10 SERDES6G Data Inversion 3.4.11 SERDES6G Signal Detection Enhancements 3.4.12 High-Speed I/O Configuration Bus 3.5 Copper Transceivers 3.5.1 Register Access 3.5.2 Cat5 Twisted Pair Media Interface 3.5.3 Wake-On-LAN and SecureOn 3.5.4 Ethernet Inline Powered Devices 3.5.5 IEEE 802.3af PoE Support 3.5.6 ActiPHY™ Power Management 3.5.7 Testing Features 3.5.8 VeriPHY™ Cable Diagnostics 3.6 Statistics 3.6.1 Port Statistics 3.6.2 Accessing and Clearing Counters 3.7 Basic Classifier 3.7.1 General Data Extraction Setup 3.7.2 Frame Acceptance Filtering 3.7.3 QoS, DP, and DSCP Classification 3.7.4 VLAN Classification 3.7.5 Link Aggregation Code Generation 3.7.6 CPU Forwarding Determination 3.8 VCAP 3.8.1 Port Configuration 3.8.2 VCAP IS1 3.8.3 VCAP IS2 3.8.4 VCAP ES0 3.8.5 Range Checkers 3.8.6 VCAP Configuration 3.8.7 Advanced VCAP Operations 3.9 Analyzer 3.9.1 MAC Table 3.9.2 VLAN Table 3.9.3 Forwarding Engine 3.9.4 Analyzer Monitoring 3.10 Policers 3.10.1 Policer Allocation 3.10.2 Policer Burst and Rate Configuration 3.11 Shared Queue System 3.11.1 Buffer Management 3.11.2 Frame Reference Management 3.11.3 Resource Depletion Condition 3.11.4 Configuration Example 3.11.5 Watermark Programming and Consumption Monitoring 3.11.6 Advanced Resource Management 3.11.7 Ingress Pause Request Generation 3.11.8 Tail Dropping 3.11.9 Test Utilities 3.11.10 Energy Efficient Ethernet 3.12 Scheduler and Shapers 3.12.1 Scheduler Element 3.12.2 Egress Shapers 3.12.3 Deficit Weighted Round Robin 3.12.4 Round Robin 3.12.5 Shaping and DWRR Scheduling Examples 3.13 Rewriter 3.13.1 VLAN Editing 3.13.2 DSCP Remarking 3.13.3 FCS Updating 3.13.4 PTP Time Stamping 3.13.5 Special Rewriter Operations 3.14 CPU Port Module 3.14.1 Frame Extraction 3.14.2 Frame Injection 3.14.3 Node Processor Interface (NPI) 3.14.4 Frame Generation Engine for Periodic Transmissions 3.15 VRAP Engine 3.15.1 VRAP Request Frame Format 3.15.2 VRAP Response Frame Format 3.15.3 VRAP Header Format 3.15.4 VRAP READ Command 3.15.5 VRAP WRITE Command 3.15.6 VRAP READ-MODIFY-WRITE Command 3.15.7 VRAP IDLE Command 3.15.8 VRAP PAUSE Command 3.16 Layer 1 Timing 3.17 Hardware Time Stamping 3.17.1 Time Stamp Classification 3.17.2 Time of Day Generation 3.17.3 Hardware Time Stamping Module 3.17.4 Configuring I/O Delays 3.18 Clocking and Reset 3.18.1 Pin Strapping 4 VCore-Ie System and CPU Interfaces 4.1 VCore-Ie Configurations 4.2 Clocking and Reset 4.2.1 Watchdog Timer 4.3 Shared Bus 4.3.1 VCore-Ie Shared Bus Arbitration 4.3.2 Chip Register Region 4.3.3 SI Flash Region 4.3.4 PCIe Region 4.3.5 Starting the VCore-Ie CPU 4.3.6 Accessing the VCore-Ie Shared Bus 4.3.7 Paged Access to VCore-Ie Shared Bus 4.3.8 Software Debug and Development 4.4 VCore-Ie CPU 4.5 Load on-chip memory with code-image. For more information, see External CPU Support 4.5.1 Register Access and Multimaster Systems 4.5.2 Serial Interface in Slave Mode 4.5.3 MIIM Interface in Slave Mode 4.5.4 Access to the VCore Shared Bus 4.5.5 Mailbox and Semaphores 4.6 PCIe Endpoint Controller 4.6.1 Accessing Endpoint Registers 4.6.2 Enabling the Endpoint 4.6.3 Base Address Registers Inbound Requests 4.6.4 Outbound Interrupts 4.6.5 Outbound Access 4.6.6 Power Management 4.6.7 Device Reset Using PCIe 4.7 Frame DMA 4.7.1 DMA Control Block Structures 4.7.2 Enabling and Disabling FDMA Channels 4.7.3 Channel Counters 4.7.4 FDMA Events and Interrupts 4.7.5 FDMA Extraction 4.7.6 FDMA Injection 4.7.7 Manual Mode 4.8 VCore-Ie System Peripherals 4.8.1 SI Boot Controller 4.8.2 SI Master Controller 4.8.3 Timers 4.8.4 UARTs 4.8.5 Two-Wire Serial Interface 4.8.6 MII Management Controller 4.8.7 GPIO Controller 4.8.8 Serial GPIO Controller 4.8.9 Fan Controller 4.8.10 Temperature Sensor 4.8.11 Memory Integrity Monitor 4.8.12 Interrupt Controller 5 Features 5.1 Switch Control 5.1.1 Switch Initialization 5.2 Port Module Control 5.2.1 Port Reset Procedure 5.2.2 Port Counters 5.3 Layer-2 Switch 5.3.1 Basic Switching 5.3.2 Standard VLAN Operation 5.3.3 Provider Bridges and Q-in-Q Operation 5.3.4 Private VLANs 5.3.5 Asymmetric VLANs 5.3.6 Spanning Tree Protocols 5.3.7 IEEE 802.1X: Network Access Control 5.3.8 Link Aggregation 5.3.9 Simple Network Management Protocol (SNMP) 5.3.10 Mirroring 5.4 IGMP and MLD Snooping 5.4.1 IGMP and MLD Snooping Configuration 5.4.2 IP Multicast Forwarding Configuration 5.5 Quality of Service (QoS) 5.5.1 Basic QoS Configuration 5.5.2 IPv4 and IPv6 DSCP Remarking 5.5.3 Voice over IP (VoIP) 5.6 VCAP Applications 5.6.1 Notation for Control Lists Entries 5.6.2 Ingress Control Lists 5.6.3 Access Control Lists 5.6.4 Source IP Filter (SIP Filter) 5.6.5 DHCP Application 5.6.6 ARP Filtering 5.6.7 Ping Policing 5.6.8 TCP SYN Policing 5.7 CPU Extraction and Injection 5.7.1 Forwarding to CPU 5.7.2 Frame Extraction 5.7.3 Frame Injection 5.7.4 Frame Extraction and Injection Using An External CPU 6 Registers 7 Electrical Specifications 7.1 DC Specifications 7.1.1 Internal Pull-Up or Pull-Down Resistors 7.1.2 Reference Clock Inputs 7.1.3 PLL Clock Outputs 7.1.4 SERDES1G 7.1.5 SERDES6G 7.1.6 GPIO, SI, JTAG, and Miscellaneous Signals 7.1.7 Thermal Diode 7.2 AC Specifications 7.2.1 REFCLK Reference Clock (1G and 6G Serdes) 7.2.2 PLL Clock Outputs 7.2.3 SERDES1G 7.2.4 SERDES6G 7.2.5 Reset Timing Specifications 7.2.6 MIIM Timing Specifications 7.2.7 SI Boot Timing Master Mode Specifications 7.2.8 SI Timing Master Mode Specifications 7.2.9 SI Timing Slave Mode Specifications 7.2.10 JTAG Interface Specifications 7.2.11 Serial I/O Timing Specifications 7.2.12 Recovered Clock Outputs Specifications 7.2.13 Two-Wire Serial Interface Specifications 7.2.14 IEEE1588 Time Tick Output Specifications 7.3 Current and Power Consumption 7.4 Operating Conditions 7.4.1 Power Supply Sequencing 7.5 Stress Ratings 8 Pin Descriptions 8.1 Pin Diagram 8.2 Pins by Function 9 Package Information 9.1 Package Drawing 9.2 Thermal Specifications 9.3 Moisture Sensitivity 10 Design Guidelines 10.1 Power Supplies 10.2 Power Supply Decoupling 10.2.1 Reference Clock 10.2.2 Single-Ended REFCLK Input 10.3 Interfaces 10.3.1 General Recommendations 10.3.2 SerDes Interfaces (SGMII, 2.5GQSGMII) 10.3.3 Serial Interface 10.3.4 PCI Express Interface 10.3.5 Two-Wire Serial Interface 10.3.6 DDR3 SDRAM Interface 10.3.7 Thermal Diode External Connection 11 Ordering Information
10.3.5 Two-Wire Serial Interface
The two-wire serial interface is capable of suppressing small amplitude glitches. The duration of the glitch which can be suppressed is set in register ICPU_CFG::TWI_SPIKE_FILTER_CFG. The default value of 0 will suppress a 4ns glitch. It is recommended that SPIKE_FILTER_CFG be set to 12, which will suppress a 52ns glitch.
10.3.6 DDR3 SDRAM Interface
The DDR3 SDRAM interface is designed to interface with 8-bit or 16-bit DDR SDRAM devices. The maximum amount of physical memory that can be addressed is one gigabyte. Possible combinations of memory modules are: • One 8-bit device, connect to CS0 byte lane 0. • Two 8-bit devices, connect to CS0 and both byte lanes. • Four 8-bit devices, connect to both chip-selects and both byte lanes. • One 16-bit device, connect to CS0 and both byte lanes. • Two 16-bit devices, connect to both chip-selects and both byte lanes. When using a single 8-bit device, the memory controller must be configured for 8-bit mode. All other configurations use 16-bit mode. All signals on this interface must be connected one-to-one with the corresponding signals on the DDR SDRAM device. When using only one 8-bit device, the DDR_UDQS, DDR_UDQSn, DDR_UDM, and DDR_DQ[15:8] signals must be left unconnected. When using DDR2 SDRAM devices that has only four banks, the DDR_BA[2] signal must be left unconnected. When using four 8-bit devices or two 16-bit devices, the CS1 memory modules must be placed in- between the VSC7511 device and the CS0 memory modules so that the DDR-DQS, DDR-DM, and DDR_DQ signals pass the CS1 devices first before reaching the CS0 devices. The placement of the VSC7511 interface signals is optimized for point-to-point routing directly to a single DDR3 16-bit SDRAM.
Figure 109 • 16-Bit DDR3 SDRAM Point-to-Point Routing
Data Lane Address DRAM Switch Clock Device Address Because reflections are absorbed by the devices, keep the physical distance of all the SDRAM interface signals as low as possible. Omit external discrete termination on the address, command, control, and clock lines. When routing the DDR interface, attention must be paid to the skew, primary concern is skew within the byte lane between the differential strobe and the single-ended signals. Skew recommendations for the DDR interface are listed in the following table.
Table 249 • Recommended Skew Budget Description Signal Maximum Skew
Skew within byte lane 0 DDR_LDQS/DDR_LDQSn 50 ps Skew within byte lane 1 DDR_UDQS/DDR_UDQSn 50 ps VMDS-10488 VSC7511 Datasheet Revision 4.2 306 Document Outline 1 Revision History 1.1 Revision 4.2 1.2 Revision 4.1 1.3 Revision 4.0 1.4 Revision 2.1 1.5 Revision 2.0 2 Product Overview 2.1 General Features 2.1.1 Layer 2 Switching 2.1.2 Layer 2 Multicast 2.1.3 Quality of Service 2.1.4 Security 2.1.5 Management 2.1.6 Product Parameters 2.2 Applications 2.3 Functional Overview 2.3.1 Frame Arrival 2.3.2 Basic and Advanced Frame Classification 2.3.3 Versatile Content Aware Processor (VCAP) 2.3.4 Policing 2.3.5 Layer-2 Forwarding 2.3.6 Shared Queue System and Egress Scheduler 2.3.7 Rewriter and Frame Departure 2.3.8 CPU Port Module 2.3.9 Synchronous Ethernet and Precision Time Protocol 2.3.10 CPU System and Interfaces 3 Functional Descriptions 3.1 Port Numbering and Mappings 3.1.1 Supported SerDes Interfaces 3.1.2 PCIe Mode 3.1.3 Logical Port Numbers 3.2 Port Modules 3.2.1 MAC 3.2.2 PCS 3.3 SERDES1G 3.3.1 SERDES1G Basic Configuration 3.3.2 SERDES1G Loopback Modes 3.3.3 Synchronous Ethernet 3.3.4 SERDES1G Deserializer Configuration 3.3.5 SERDES1G Serializer Configuration 3.3.6 SERDES1G Input Buffer Configuration 3.3.7 SERDES1G Output Buffer Configuration 3.3.8 SERDES1G Clock and Data Recovery (CDR) in 100BASE-FX 3.3.9 Energy Efficient Ethernet 3.3.10 SERDES1G Data Inversion 3.4 SERDES6G 3.4.1 SERDES6G Basic Configuration 3.4.2 SERDES6G Loopback Modes 3.4.3 Synchronous Ethernet 3.4.4 SERDES6G Deserializer Configuration 3.4.5 SERDES6G Serializer Configuration 3.4.6 SERDES6G Input Buffer Configuration 3.4.7 SERDES6G Output Buffer Configuration 3.4.8 SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX 3.4.9 Energy Efficient Ethernet 3.4.10 SERDES6G Data Inversion 3.4.11 SERDES6G Signal Detection Enhancements 3.4.12 High-Speed I/O Configuration Bus 3.5 Copper Transceivers 3.5.1 Register Access 3.5.2 Cat5 Twisted Pair Media Interface 3.5.3 Wake-On-LAN and SecureOn 3.5.4 Ethernet Inline Powered Devices 3.5.5 IEEE 802.3af PoE Support 3.5.6 ActiPHY™ Power Management 3.5.7 Testing Features 3.5.8 VeriPHY™ Cable Diagnostics 3.6 Statistics 3.6.1 Port Statistics 3.6.2 Accessing and Clearing Counters 3.7 Basic Classifier 3.7.1 General Data Extraction Setup 3.7.2 Frame Acceptance Filtering 3.7.3 QoS, DP, and DSCP Classification 3.7.4 VLAN Classification 3.7.5 Link Aggregation Code Generation 3.7.6 CPU Forwarding Determination 3.8 VCAP 3.8.1 Port Configuration 3.8.2 VCAP IS1 3.8.3 VCAP IS2 3.8.4 VCAP ES0 3.8.5 Range Checkers 3.8.6 VCAP Configuration 3.8.7 Advanced VCAP Operations 3.9 Analyzer 3.9.1 MAC Table 3.9.2 VLAN Table 3.9.3 Forwarding Engine 3.9.4 Analyzer Monitoring 3.10 Policers 3.10.1 Policer Allocation 3.10.2 Policer Burst and Rate Configuration 3.11 Shared Queue System 3.11.1 Buffer Management 3.11.2 Frame Reference Management 3.11.3 Resource Depletion Condition 3.11.4 Configuration Example 3.11.5 Watermark Programming and Consumption Monitoring 3.11.6 Advanced Resource Management 3.11.7 Ingress Pause Request Generation 3.11.8 Tail Dropping 3.11.9 Test Utilities 3.11.10 Energy Efficient Ethernet 3.12 Scheduler and Shapers 3.12.1 Scheduler Element 3.12.2 Egress Shapers 3.12.3 Deficit Weighted Round Robin 3.12.4 Round Robin 3.12.5 Shaping and DWRR Scheduling Examples 3.13 Rewriter 3.13.1 VLAN Editing 3.13.2 DSCP Remarking 3.13.3 FCS Updating 3.13.4 PTP Time Stamping 3.13.5 Special Rewriter Operations 3.14 CPU Port Module 3.14.1 Frame Extraction 3.14.2 Frame Injection 3.14.3 Node Processor Interface (NPI) 3.14.4 Frame Generation Engine for Periodic Transmissions 3.15 VRAP Engine 3.15.1 VRAP Request Frame Format 3.15.2 VRAP Response Frame Format 3.15.3 VRAP Header Format 3.15.4 VRAP READ Command 3.15.5 VRAP WRITE Command 3.15.6 VRAP READ-MODIFY-WRITE Command 3.15.7 VRAP IDLE Command 3.15.8 VRAP PAUSE Command 3.16 Layer 1 Timing 3.17 Hardware Time Stamping 3.17.1 Time Stamp Classification 3.17.2 Time of Day Generation 3.17.3 Hardware Time Stamping Module 3.17.4 Configuring I/O Delays 3.18 Clocking and Reset 3.18.1 Pin Strapping 4 VCore-Ie System and CPU Interfaces 4.1 VCore-Ie Configurations 4.2 Clocking and Reset 4.2.1 Watchdog Timer 4.3 Shared Bus 4.3.1 VCore-Ie Shared Bus Arbitration 4.3.2 Chip Register Region 4.3.3 SI Flash Region 4.3.4 PCIe Region 4.3.5 Starting the VCore-Ie CPU 4.3.6 Accessing the VCore-Ie Shared Bus 4.3.7 Paged Access to VCore-Ie Shared Bus 4.3.8 Software Debug and Development 4.4 VCore-Ie CPU 4.5 Load on-chip memory with code-image. For more information, see External CPU Support 4.5.1 Register Access and Multimaster Systems 4.5.2 Serial Interface in Slave Mode 4.5.3 MIIM Interface in Slave Mode 4.5.4 Access to the VCore Shared Bus 4.5.5 Mailbox and Semaphores 4.6 PCIe Endpoint Controller 4.6.1 Accessing Endpoint Registers 4.6.2 Enabling the Endpoint 4.6.3 Base Address Registers Inbound Requests 4.6.4 Outbound Interrupts 4.6.5 Outbound Access 4.6.6 Power Management 4.6.7 Device Reset Using PCIe 4.7 Frame DMA 4.7.1 DMA Control Block Structures 4.7.2 Enabling and Disabling FDMA Channels 4.7.3 Channel Counters 4.7.4 FDMA Events and Interrupts 4.7.5 FDMA Extraction 4.7.6 FDMA Injection 4.7.7 Manual Mode 4.8 VCore-Ie System Peripherals 4.8.1 SI Boot Controller 4.8.2 SI Master Controller 4.8.3 Timers 4.8.4 UARTs 4.8.5 Two-Wire Serial Interface 4.8.6 MII Management Controller 4.8.7 GPIO Controller 4.8.8 Serial GPIO Controller 4.8.9 Fan Controller 4.8.10 Temperature Sensor 4.8.11 Memory Integrity Monitor 4.8.12 Interrupt Controller 5 Features 5.1 Switch Control 5.1.1 Switch Initialization 5.2 Port Module Control 5.2.1 Port Reset Procedure 5.2.2 Port Counters 5.3 Layer-2 Switch 5.3.1 Basic Switching 5.3.2 Standard VLAN Operation 5.3.3 Provider Bridges and Q-in-Q Operation 5.3.4 Private VLANs 5.3.5 Asymmetric VLANs 5.3.6 Spanning Tree Protocols 5.3.7 IEEE 802.1X: Network Access Control 5.3.8 Link Aggregation 5.3.9 Simple Network Management Protocol (SNMP) 5.3.10 Mirroring 5.4 IGMP and MLD Snooping 5.4.1 IGMP and MLD Snooping Configuration 5.4.2 IP Multicast Forwarding Configuration 5.5 Quality of Service (QoS) 5.5.1 Basic QoS Configuration 5.5.2 IPv4 and IPv6 DSCP Remarking 5.5.3 Voice over IP (VoIP) 5.6 VCAP Applications 5.6.1 Notation for Control Lists Entries 5.6.2 Ingress Control Lists 5.6.3 Access Control Lists 5.6.4 Source IP Filter (SIP Filter) 5.6.5 DHCP Application 5.6.6 ARP Filtering 5.6.7 Ping Policing 5.6.8 TCP SYN Policing 5.7 CPU Extraction and Injection 5.7.1 Forwarding to CPU 5.7.2 Frame Extraction 5.7.3 Frame Injection 5.7.4 Frame Extraction and Injection Using An External CPU 6 Registers 7 Electrical Specifications 7.1 DC Specifications 7.1.1 Internal Pull-Up or Pull-Down Resistors 7.1.2 Reference Clock Inputs 7.1.3 PLL Clock Outputs 7.1.4 SERDES1G 7.1.5 SERDES6G 7.1.6 GPIO, SI, JTAG, and Miscellaneous Signals 7.1.7 Thermal Diode 7.2 AC Specifications 7.2.1 REFCLK Reference Clock (1G and 6G Serdes) 7.2.2 PLL Clock Outputs 7.2.3 SERDES1G 7.2.4 SERDES6G 7.2.5 Reset Timing Specifications 7.2.6 MIIM Timing Specifications 7.2.7 SI Boot Timing Master Mode Specifications 7.2.8 SI Timing Master Mode Specifications 7.2.9 SI Timing Slave Mode Specifications 7.2.10 JTAG Interface Specifications 7.2.11 Serial I/O Timing Specifications 7.2.12 Recovered Clock Outputs Specifications 7.2.13 Two-Wire Serial Interface Specifications 7.2.14 IEEE1588 Time Tick Output Specifications 7.3 Current and Power Consumption 7.4 Operating Conditions 7.4.1 Power Supply Sequencing 7.5 Stress Ratings 8 Pin Descriptions 8.1 Pin Diagram 8.2 Pins by Function 9 Package Information 9.1 Package Drawing 9.2 Thermal Specifications 9.3 Moisture Sensitivity 10 Design Guidelines 10.1 Power Supplies 10.2 Power Supply Decoupling 10.2.1 Reference Clock 10.2.2 Single-Ended REFCLK Input 10.3 Interfaces 10.3.1 General Recommendations 10.3.2 SerDes Interfaces (SGMII, 2.5GQSGMII) 10.3.3 Serial Interface 10.3.4 PCI Express Interface 10.3.5 Two-Wire Serial Interface 10.3.6 DDR3 SDRAM Interface 10.3.7 Thermal Diode External Connection 11 Ordering Information
