Datasheet ADP1071-1, ADP1071-2 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Isolated Synchronous Flyback Controller with Integrated iCoupler |
| Pages / Page | 27 / 10 — ADP1071-1. /ADP1071-2. Data Sheet. AGND1. AGND2. VREG1. VREG2. ADP1071-2. … |
| Revision | B |
| File Format / Size | PDF / 577 Kb |
| Document Language | English |
ADP1071-1. /ADP1071-2. Data Sheet. AGND1. AGND2. VREG1. VREG2. ADP1071-2. MODE. VDD2. VIN. TOP VIEW. (TERMINAL SIDE DOWN). OVP. Not to Scale. COMP
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ADP1071-1 /ADP1071-2 Data Sheet TE TE NC NC GA SR NC NC NC NC GA SR NC NC 3 2 1 24 23 22 3 2 1 24 23 22 AGND1 4 21 AGND2 AGND1 4 21 AGND2 VREG1 5 20 VREG2 VREG1 5 20 VREG2 ADP1071-1 ADP1071-2 MODE 6 19 VDD2 VIN 6 19 VDD2 TOP VIEW TOP VIEW EN 7 (TERMINAL SIDE DOWN) 18 OVP EN 7 (TERMINAL SIDE DOWN) 18 OVP Not to Scale Not to Scale CS 8 17 FB CS 8 17 FB RT 9 16 COMP EPAD1 EPAD2 RT 9 16 COMP EPAD1 EPAD2 10 11 12 13 14 15 10 11 12 13 14 15 C C NC NC NC NC SS2 NC NC NC NC SS2 SYN SYN NOTES NOTES 1. NC = NO CONNECT. 1. NC = NO CONNECT.
004 005
2. EPAD1 AND EPAD2 ARE INTERNALLY TIED TO 2. EPAD1 AND EPAD2 ARE INTERNALLY TIED TO AGND1 AND AGND2, RESPECTIVELY. AGND1 AND AGND2, RESPECTIVELY.
15626- 15626- Figure 4. ADP1071-1 LGA Pin Configuration Figure 5. ADP1071-2 LGA Pin Configuration
Table 10. Pin Function Descriptions, LGA Pin No. ADP1071-1 ADP1071-2 Mnemonic Description
1 1 GATE Driver Output for the Main Power MOSFET on the Primary Side. GATE is a multifunction pin. Connect a resistor from the GATE pin to AGND1 to set up the open loop soft start time. 2 2 NC No Connect. 3 3 NC No Connect. 4 4 AGND1 Ground for the Primary Side. 5 5 VREG1 8 V Regulated LDO Output for the MOSFET Driver. Connect 1 µF or greater from VREG1 to AGND1. 6 Not MODE Light Load Mode Pin (ADP1071-1 Only). This pin sets the light load mode threshold. Connect the applicable MODE pin to either AGND1 to enable forced continuous conduction mode (CCM), or to a high logic (2.5 V or higher) to force an LLM operation, or to a resistor to set up an LLM threshold voltage. Not 6 VIN Input Voltage (ADP1071-2 Only). See the Primary Side Supply, Input Voltage, and LDO section. applicable Connect a 4.7 µF capacitor to the VIN pin. The size of this capacitor can be reduced if the input voltage to the VIN pin is guaranteed stable. Reference the VIN pin to AGND1. 7 7 EN Precision Enable Input. The controller is enabled when EN is above the EN threshold voltage. The EN pin also has a programmable EN hysteresis. The EN pin is referenced to AGND1. 8 8 CS Input Current Sensing. The CS pin senses the input PWM current. Place a current sense resistor between the source terminal of the power MOSFET and AGND1.The current sense resistor sets up the input current limit. This pin is also used for the external slope compensator. Connect a resistor from the CS pin to the current sense resistor to generate a voltage ramp for the slope compensation. Reference the CS pin to AGND1. Connect a 33 pF to 100 pF capacitor at the CS pin to act as a resistor capacitor (RC) filter along with the slope compensation resistor in noisy environments. 9 9 RT Switching Period Resistor. Connect a resistor from the RT pin to AGND1 to set the oscillator frequency. 10 10 SYNC Frequency Synchronization. Connect an external clock to the SYNC pin to synchronize the internal oscillator to this external clock frequency. Connect the SYNC pin to AGND1 if this feature is not used. The SYNC frequency is recommended to be within 10% of the frequency set by the RT pin. 11 11 NC No Connect. 12 12 NC No Connect. 13 13 NC No Connect. 14 14 NC No Connect. 15 15 SS2 Soft Start on the Secondary Side. Connect a capacitor from SS2 to AGND2 to set up the soft start time on the secondary side. 16 16 COMP Compensation Node on the Secondary Side. This pin is the output of the transconductance (gm) amplifier. Reference the COMP pin to AGND2. 17 17 FB Feedback Node on the Secondary Side. Set up the resistive divider from the output voltage such that the nominal voltage, when the power supply is in regulation, is 1.2 V. Reference the FB pin to AGND2. Rev. B | Page 10 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Insulation and Safety Related Specifications Regulatory Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Detailed Block Diagram Primary Side Supply, Input Voltage, and LDO Secondary Side Supply and LDO Precision Enable Soft Start Procedure Output Voltage Sensing and Feedback Loop Compensation and Steady State Operation Slope Compensation Input/Output Current-Limit Protection Temperature Sensing Frequency Setting (RT Pin) Maximum Duty Cycle Frequency Synchronization Synchronous Rectifier (SR) Driver Output Overvoltage Protection (OVP) SR Dead Time Light Load Mode (LLM) and Continuous Conduction Mode (CCM) Soft Stop OCP/Feedback Recovery Output Voltage Tracking Remote System Reset OCP Counter External Start-Up Circuit Insulation Lifetime Layout Guidelines Applications Information Typical Application Circuits Outline Dimensions Ordering Guide
ADP1071-1 /ADP1071-2 Data Sheet TE TE NC NC GA SR NC NC NC NC GA SR NC NC 3 2 1 24 23 22 3 2 1 24 23 22 AGND1 4 21 AGND2 AGND1 4 21 AGND2 VREG1 5 20 VREG2 VREG1 5 20 VREG2 ADP1071-1 ADP1071-2 MODE 6 19 VDD2 VIN 6 19 VDD2 TOP VIEW TOP VIEW EN 7 (TERMINAL SIDE DOWN) 18 OVP EN 7 (TERMINAL SIDE DOWN) 18 OVP Not to Scale Not to Scale CS 8 17 FB CS 8 17 FB RT 9 16 COMP EPAD1 EPAD2 RT 9 16 COMP EPAD1 EPAD2 10 11 12 13 14 15 10 11 12 13 14 15 C C NC NC NC NC SS2 NC NC NC NC SS2 SYN SYN NOTES NOTES 1. NC = NO CONNECT. 1. NC = NO CONNECT.
004 005
2. EPAD1 AND EPAD2 ARE INTERNALLY TIED TO 2. EPAD1 AND EPAD2 ARE INTERNALLY TIED TO AGND1 AND AGND2, RESPECTIVELY. AGND1 AND AGND2, RESPECTIVELY.
15626- 15626- Figure 4. ADP1071-1 LGA Pin Configuration Figure 5. ADP1071-2 LGA Pin Configuration
Table 10. Pin Function Descriptions, LGA Pin No. ADP1071-1 ADP1071-2 Mnemonic Description
1 1 GATE Driver Output for the Main Power MOSFET on the Primary Side. GATE is a multifunction pin. Connect a resistor from the GATE pin to AGND1 to set up the open loop soft start time. 2 2 NC No Connect. 3 3 NC No Connect. 4 4 AGND1 Ground for the Primary Side. 5 5 VREG1 8 V Regulated LDO Output for the MOSFET Driver. Connect 1 µF or greater from VREG1 to AGND1. 6 Not MODE Light Load Mode Pin (ADP1071-1 Only). This pin sets the light load mode threshold. Connect the applicable MODE pin to either AGND1 to enable forced continuous conduction mode (CCM), or to a high logic (2.5 V or higher) to force an LLM operation, or to a resistor to set up an LLM threshold voltage. Not 6 VIN Input Voltage (ADP1071-2 Only). See the Primary Side Supply, Input Voltage, and LDO section. applicable Connect a 4.7 µF capacitor to the VIN pin. The size of this capacitor can be reduced if the input voltage to the VIN pin is guaranteed stable. Reference the VIN pin to AGND1. 7 7 EN Precision Enable Input. The controller is enabled when EN is above the EN threshold voltage. The EN pin also has a programmable EN hysteresis. The EN pin is referenced to AGND1. 8 8 CS Input Current Sensing. The CS pin senses the input PWM current. Place a current sense resistor between the source terminal of the power MOSFET and AGND1.The current sense resistor sets up the input current limit. This pin is also used for the external slope compensator. Connect a resistor from the CS pin to the current sense resistor to generate a voltage ramp for the slope compensation. Reference the CS pin to AGND1. Connect a 33 pF to 100 pF capacitor at the CS pin to act as a resistor capacitor (RC) filter along with the slope compensation resistor in noisy environments. 9 9 RT Switching Period Resistor. Connect a resistor from the RT pin to AGND1 to set the oscillator frequency. 10 10 SYNC Frequency Synchronization. Connect an external clock to the SYNC pin to synchronize the internal oscillator to this external clock frequency. Connect the SYNC pin to AGND1 if this feature is not used. The SYNC frequency is recommended to be within 10% of the frequency set by the RT pin. 11 11 NC No Connect. 12 12 NC No Connect. 13 13 NC No Connect. 14 14 NC No Connect. 15 15 SS2 Soft Start on the Secondary Side. Connect a capacitor from SS2 to AGND2 to set up the soft start time on the secondary side. 16 16 COMP Compensation Node on the Secondary Side. This pin is the output of the transconductance (gm) amplifier. Reference the COMP pin to AGND2. 17 17 FB Feedback Node on the Secondary Side. Set up the resistive divider from the output voltage such that the nominal voltage, when the power supply is in regulation, is 1.2 V. Reference the FB pin to AGND2. Rev. B | Page 10 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Insulation and Safety Related Specifications Regulatory Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Detailed Block Diagram Primary Side Supply, Input Voltage, and LDO Secondary Side Supply and LDO Precision Enable Soft Start Procedure Output Voltage Sensing and Feedback Loop Compensation and Steady State Operation Slope Compensation Input/Output Current-Limit Protection Temperature Sensing Frequency Setting (RT Pin) Maximum Duty Cycle Frequency Synchronization Synchronous Rectifier (SR) Driver Output Overvoltage Protection (OVP) SR Dead Time Light Load Mode (LLM) and Continuous Conduction Mode (CCM) Soft Stop OCP/Feedback Recovery Output Voltage Tracking Remote System Reset OCP Counter External Start-Up Circuit Insulation Lifetime Layout Guidelines Applications Information Typical Application Circuits Outline Dimensions Ordering Guide
