Datasheet AD74413R (Analog Devices) - 58

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AD74413R Data Sheet Bits Bit Name Description Reset Access
[4:3] EN_50_60_HZ Enables the 50 Hz and 60 Hz rejection and sets the ADC conversion rate for channel 0x0 R/W conversions. There is a separate bit in the ADC_CONV_CTRL register that sets the conversion rates for the diagnostic conversions. 00: enables the 50 Hz and 60 Hz rejection, resulting in a sampling rate of 20 SPS. 01: disables the 50 Hz and 60 Hz rejection, resulting in a sampling rate of 4.8 kSPS. 10: enables the 50 Hz and 60 Hz rejection and HART noise rejection, resulting in a sampling rate of 10 SPS. 11: disables the 50 Hz and 60 Hz rejection, resulting in a sampling rate of 1.2 kSPS. 2 CH_200K_TO_GND Enables the 200 kΩ resistor to ground. This bit is set to 0 when the corresponding 0x0 R/W CH_FUNC_SETUPx register is programmed, irrespective of the function. [1:0] ADC_MUX Selects the ADC input node. Values outside of those listed in this table select the voltage 0x0 R/W across the I/OP_x to I/ON_x screw terminals. These bits may change when the corresponding CH_FUNC_SETUPx register is written to. 00: voltage between the I/OP_x screw terminals and the AGND_SENSE pin. 01: voltage across the 100 Ω resistor. Typically used to measure the current.
DIGITAL INPUT CONFIGURATION REGISTER PER CHANNEL Address: 0x09 to 0x0C (Increments of 0x01), Reset: 0x000B, Name: DIN_CONFIGx
These four registers configure the digital input for each channel.
Table 32. Bit Descriptions for DIN_CONFIGx Bits Bit Name Description Reset Access
15 COUNT_EN Enables DIN count. If INV_DIN_COMP_OUT is 0, the positive edges of the debounced 0x0 R/W DIN are counted. If INV_DIN_COMP_OUT is 1, the negative edges of the debounced DIN are counted. The count is reflected in the DIN_COUNTERx register. 14 COMP_INPUT_FILTERED Set to 0 to select the unfiltered input to the comparator on the SENSELF_x pin. 0x0 R/W Set to 1 to select the filtered input to the comparator on the SENSELF_x pin. 13 INV_DIN_COMP_OUT Set to 1 to invert the output from the digital input comparator. 0x0 R/W 12 COMPARATOR_EN Set to 1 to enable the comparator. This bit may change when the corresponding 0x0 R/W CH_FUNC_SETUPx register is programmed. 11 DIN_RANGE Selects the DIN_SINK current range. 0x0 R/W 0: Range 0. See Table 7 for typical range, resolution, and series resistance values. 1: Range 1. See Table 7 for typical range, resolution, and series resistance values. [10:6] DIN_SINK Sets the sink current in digital input logic mode. These bits allow the current to be 0x0 R/W programmed within the range selected by the DIN_RANGE bit. Set the DIN_SINK bits to 0x00 to turn off the current sink. Note that these bits are set to 0 when the corresponding CH_FUNC_SETUPx register is written to, irrespective of the function. 5 DEBOUNCE_MODE This bit determines how the digital input debounce logic operates as described in 0x0 R/W the Digital Input Logic section. 0: Debounce Mode 0. Integrator method is used. A counter increments when the comparator input is asserted and decrements when the signal is deasserted. 1: Debounce Mode 1. A simple counter increments while a signal is asserted, and the counter value resets when the signal deasserts. [4:0] DEBOUNCE_TIME These bits configure the debounce time in the digital input modes. Reset the value 0xB R/W for these bits to 240 μs. Set DEBOUNCE_TIME to 0x0 to bypass the debounce circuit. Rev. 0 | Page 58 of 70 Document Outline Features Applications General Description Companion Products Product Highlights Revision History Functional Block Diagram Specifications Voltage Output Current Output Voltage Input Current Input Externally Powered and Current Input Externally Powered with HART Current Input Loop Powered Resistance Measurement Digital Input Logic Digital Input Loop Powered ADC Specifications General Specifications Timing Characteristics SPI Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Digital Input Resistance Measurement Reference ADC Supplies Theory of Operation Robust Architecture Serial Interface DAC Architecture ADC Overview Reference Reference Noise Charge Pump Power-On State of the AD74413R Device Functions High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpreting ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data HART Compatibility Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Thermocouple Measurement Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Externally Powered with HART Compatibility Mode Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered with HART Compatibility Mode Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Threshold Setting Digital Input Current Sink Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter Digital Input Counter Digital Input, Loop Powered Mode Interpreting ADC Data Getting Started Using Channel Functions Switching Channel Functions ADC Functionality ADC Conversion Rates ADC_RDYb Functionality ADC Output Data Format ADC Noise Diagnostics DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control HART Compliant Slew Driving Inductive Loads Reset Function Thermal Alert and Thermal Reset Faults and Alerts Channel Faults Power Supply Monitors GPO_x Pins SPI Interface and Diagnostics SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback Board Design and Layout Considerations Applications Information Register Map NOP Register Function Setup Register per Channel ADC Configuration Register per Channel Digital Input Configuration Register per Channel GPO Parallel Data Register GPO Configuration Register per Channel Output Configuration Register per Channel DAC Code Register per Channel DAC Clear Code Register per Channel DAC Active Code Register per Channel Digital Input Threshold Register ADC Conversion Control Register Diagnostics Select Register Digital Output Level Register ADC Conversion Results Register per Channel Diagnostic Results Registers per Diagnostic Channel Alert Status Register Live Status Register Alert Mask Register Debounced DIN Count Register per Channel Readback Select Register Thermal Reset Enable Register Command Register Scratch or Spare Register Silicon Revision Register Outline Dimensions Ordering Guide