Datasheet AD74412R (Analog Devices) - 29

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Data Sheet AD74412R Voltage Output Mode Interpreting ADC Data
The voltage output amplifier can generate unipolar voltages up In voltage output mode, the ADC, by default, measures the to 11 V. An internal low voltage charge pump al ows the amplifier current through the RSENSE in a −25 mA to +25 mA range. Use to generate a true zero output voltage. The voltage on the low- the ADC measurement result to calculate the current through side of the RSENSE is sensed on the SENSEL_x pin via a 2 kΩ the RSENSE with the fol owing equation: resistor, which closes the feedback loop and maintains stability.   ADC _CODE   The short-circuit limit in voltage output mode is programmable  +  × M V IN   Voltage Range    65,535 per channel. The circuit minimizes glitching on the I/OP_x  I  = R screw terminal when the AVDD supply (V SENSE SE R NSE AVDD) is ramping or when the use case configuration is changed. where: Figure 35 shows the current, voltage, and measurement paths of I is the measured current in amps. A negative current SE R NSE the voltage output mode. indicates the current is sourced from the AD74412R. A positive
Voltage Output Short-Circuit Protection
current indicates that the AD74412R is sinking the current. VMIN is the minimum voltage of the selected ADC range, which The short-circuit limit for the voltage output mode of the is −2.5 V by default. AD74412R is typical y 29 mA per channel when sourcing ADC_CODE is the value of the ADC_RESULTx registers. current. To provide flexibility for the user, a lower short-circuit Voltage Range is the full span of the ADC range, which is 5 V. limit of typical y 7 mA can be selected per channel by setting RSENSE is the RSENSE resistor, which is 100 Ω. the I_LIMIT bit in the OUTPUT_CONFIGx registers. The current limit for when the AD74412R is sinking current is typically 3.8 mA. If the selected short-circuit limit is reached on a channel, a voltage output short-circuit error is flagged for that channel and the ALERT pin asserts.
REFOUT REFIN ALDO1V8 ALDO5V AVDD MEASUREMENT PATH VOLTAGE PATH CURRENT PATH AD74412R 1.8V 5V LDO LDO IOVDD CCOMP_x DVCC VIOUTP_x 1nF VOUT SCALING CASCODE_x DLDO1V8 1.8V 2.5V INTERNAL DLDO VREF OSCILLATOR R DAC SENSE AVSS 100, 0.1% I/OP_x DGND 10ppm/°C BAV99 SCLK SENSEHF_x SYNC L SENSELF_x UX VIOUTN_x SDI ADC UX M AGND_SENSE M SDO SENSEH_x 2kΩ, 0.1% CHANNE INPUT ALERT SHIFT SENSEHF_x REGISTER ADC_RDY R CLOAD AND FILTER CFILTER 68nF DIGITAL LDAC DIAGNOSTICS SENSELF_x LOGIC BLOCK SENSEL_x 2kΩ GPO_A UX VALVE M SENSEL_x SENSELF_x GPO_B TVS R GPO_C FILTER CFILTER THRESHOLD GPO_D CHANNEL A POWER-ON CHANNEL B RESET RESET I/ON_x CHANNEL C AGND AVSS = NEGATIVE DVCC CHARGE PUMP CHANNEL D AGND1 AVSS CPUMP_N CPUMP_P AGND3 AGND2 AGND_SENSE
006
CPUMP FLY
21274-
CAPACITOR
Figure 35. Voltage Output Mode Configuration Rev. A | Page 29 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION COMPANION PRODUCTS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS VOLTAGE OUTPUT CURRENT OUTPUT VOLTAGE INPUT CURRENT INPUT EXTERNALLY POWERED CURRENT INPUT LOOP POWERED RTD MEASUREMENT DIGITAL INPUT LOGIC DIGITAL INPUT LOOP POWERED ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS SPI Timing Specifications Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT CURRENT OUTPUT REFERENCE ADC SUPPLIES THEORY OF OPERATION ROBUST ARCHITECTURE SERIAL INTERFACE DAC ARCHITECTURE ADC OVERVIEW REFERENCE Reference Noise Charge Pump POWER-ON STATE OF THE AD74412R DEVICE FUNCTIONS High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpretin ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Current Sink Digital Input Threshold Setting Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter DIGITAL INPUT, LOOP POWERED MODE Interpreting ADC Data GETTING STARTED USING CHANNEL FUNCTIONS Switching Channel Functions ADC FUNCTIONALITY ADC Conversion Rates ADC_RDYB Functionality ADC Output Data Format ADC Noise DIAGNOSTICS DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control DRIVING INDUCTIVE LOADS RESET FUNCTION THERMAL ALERT AND THERMAL RESET FAULTS AND ALERTS Channel Faults POWER SUPPLY MONITORS GPO_x PINS SPI INTERFACE AND DIAGNOSTICS SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback BOARD DESIGN AND LAYOUT CONSIDERATIONS APPLICATIONS INFORMATION REGISTER MAP NOP REGISTER FUNCTION SETUP REGISTER PER CHANNEL ADC CONFIGURATION REGISTER PER CHANNEL DIGITAL INPUT CONFIGURATION REGISTER PER CHANNEL GPO PARALLEL DATA REGISTER GPO CONFIGURATION REGISTER PER CHANNEL OUTPUT CONFIGURATION REGISTER PER CHANNEL DAC CODE REGISTER PER CHANNEL DAC CLEAR CODE REGISTER PER CHANNEL DAC ACTIVE CODE REGISTER PER CHANNEL DIGITAL INPUT THRESHOLD REGISTER ADC CONVERSION CONTROL REGISTER DIAGNOSTICS SELECT REGISTER DIGITAL OUTPUT LEVEL REGISTER ADC CONVERSION RESULTS REGISTER PER CHANNEL DIAGNOSTIC RESULTS REGISTERS PER DIAGNOSTIC CHANNEL ALERT STATUS REGISTER LIVE STATUS REGISTER ALERT MASK REGISTER READBACK SELECT REGISTER 80 SPS ADC CONVERSION CONTROL REGISTER THERMAL RESET ENABLE REGISTER COMMAND REGISTER SCRATCH OR SPARE REGISTER SILICON REVISION REGISTER OUTLINE DIMENSIONS ORDERING GUIDE