Datasheet AD74412R (Analog Devices) - 30

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AD74412R Data Sheet Current Output Mode Interpreting ADC Data
In current output mode, the DAC provides a current output on In current output mode, the ADC, by default, is configured to the VIOUTP_x pin, that is regulated by sensing the differential measures the voltage across the screw terminals (I/OP_x to voltage across RSENSE by using the SENSEL_x and SENSEH_x I/ON_x) in a 0 V to 10 V range. Use the ADC measurement pins. In addition, an optional, external P channel FET can pass result to calculate the voltage across these screw terminals by the 0 mA to 25 mA current output to lower power dissipation on using the following equation: the die in cases where a low resistive load is present. VADC = (ADC_CODE/65,535) × Voltage Range The circuit minimizes glitching on the I/OP_x screw terminal where: when the VAVDD is ramping or when the use case configuration V is changed. ADC is the measured voltage in volts. ADC_CODE is the value of the ADC_RESULTx registers. Figure 36 shows the current, voltage, and measurement paths of Voltage Range is the measurement range of the ADC and is 10 V. the current output mode.
Current Output Open Circuit Detection
In current output mode, if the headroom voltage falls below the compliance voltage (specified in Table 2), due to an open-loop circuit on any channel, a current output open circuit error is flagged for that channel and the ALERT pin asserts. If the VAVDD is insufficient to drive the programmed current output, the open circuit error is flagged.
REFOUT REFIN ALDO1V8 ALDO5V AVDD MEASUREMENT PATH VOLTAGE PATH CURRENT PATH AD74412R 1.8V 5V LDO LDO IOVDD CCOMP_x DVCC VIOUTP_x 1nF CASCODE_x OPTIONAL P CHANNEL FET 2.5V FOR LOW R DLDO1V8 1.8V LOAD INTERNAL DLDO VREF OSCILLATOR R DAC SENSE 100, 0.1% G=1 DGND 10ppm/°C I/OP_x BAV99 SCLK SENSEHF_x SYNC L SENSELF_x UX VIOUTN_x SDI ADC UX M AGND_SENSE M SDO SENSEH_x 2kΩ, 0.1% CHANNE INPUT ALERT SHIFT SENSEHF_x REGISTER ADC_RDY R CLOAD VALVE AND C FILTER FILTER 68nF DIGITAL LDAC DIAGNOSTICS SENSELF_x LOGIC BLOCK SENSEL_x 2kΩ GPO_A UX M SENSEL_x GPO_B SENSELF_x TVS R GPO_C C FILTER FILTER THRESHOLD GPO_D CHANNEL A POWER-ON CHANNEL B RESET RESET I/ON_x CHANNEL C AVSS = NEGATIVE DVCC CHARGE PUMP AGND CHANNEL D AGND1 AVSS CPUMP_N CPUMP_P AGND3 AGND2 AGND_SENSE
007
CPUMP FLY
21274-
CAPACITOR
Figure 36. Current Output Mode Configuration Rev. A | Page 30 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION COMPANION PRODUCTS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS VOLTAGE OUTPUT CURRENT OUTPUT VOLTAGE INPUT CURRENT INPUT EXTERNALLY POWERED CURRENT INPUT LOOP POWERED RTD MEASUREMENT DIGITAL INPUT LOGIC DIGITAL INPUT LOOP POWERED ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS SPI Timing Specifications Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT CURRENT OUTPUT REFERENCE ADC SUPPLIES THEORY OF OPERATION ROBUST ARCHITECTURE SERIAL INTERFACE DAC ARCHITECTURE ADC OVERVIEW REFERENCE Reference Noise Charge Pump POWER-ON STATE OF THE AD74412R DEVICE FUNCTIONS High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpretin ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Current Sink Digital Input Threshold Setting Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter DIGITAL INPUT, LOOP POWERED MODE Interpreting ADC Data GETTING STARTED USING CHANNEL FUNCTIONS Switching Channel Functions ADC FUNCTIONALITY ADC Conversion Rates ADC_RDYB Functionality ADC Output Data Format ADC Noise DIAGNOSTICS DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control DRIVING INDUCTIVE LOADS RESET FUNCTION THERMAL ALERT AND THERMAL RESET FAULTS AND ALERTS Channel Faults POWER SUPPLY MONITORS GPO_x PINS SPI INTERFACE AND DIAGNOSTICS SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback BOARD DESIGN AND LAYOUT CONSIDERATIONS APPLICATIONS INFORMATION REGISTER MAP NOP REGISTER FUNCTION SETUP REGISTER PER CHANNEL ADC CONFIGURATION REGISTER PER CHANNEL DIGITAL INPUT CONFIGURATION REGISTER PER CHANNEL GPO PARALLEL DATA REGISTER GPO CONFIGURATION REGISTER PER CHANNEL OUTPUT CONFIGURATION REGISTER PER CHANNEL DAC CODE REGISTER PER CHANNEL DAC CLEAR CODE REGISTER PER CHANNEL DAC ACTIVE CODE REGISTER PER CHANNEL DIGITAL INPUT THRESHOLD REGISTER ADC CONVERSION CONTROL REGISTER DIAGNOSTICS SELECT REGISTER DIGITAL OUTPUT LEVEL REGISTER ADC CONVERSION RESULTS REGISTER PER CHANNEL DIAGNOSTIC RESULTS REGISTERS PER DIAGNOSTIC CHANNEL ALERT STATUS REGISTER LIVE STATUS REGISTER ALERT MASK REGISTER READBACK SELECT REGISTER 80 SPS ADC CONVERSION CONTROL REGISTER THERMAL RESET ENABLE REGISTER COMMAND REGISTER SCRATCH OR SPARE REGISTER SILICON REVISION REGISTER OUTLINE DIMENSIONS ORDERING GUIDE