Datasheet AD7293 (Analog Devices) - 25
| Manufacturer | Analog Devices |
| Description | 12-Bit Power Amplifier Current Controller with ADC, DACs, Temperature and Current Sensors |
| Pages / Page | 79 / 25 — Data Sheet. AD7293. 0V TO +62.5V. 0V TO +1.25V. RS0+MON 0V TO +62.5V 0V … |
| Revision | D |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
Data Sheet. AD7293. 0V TO +62.5V. 0V TO +1.25V. RS0+MON 0V TO +62.5V 0V TO +1.25V. RS1+MON. 2N3904. RS2+MON. NPN. Dx+. 10pF. RS3+MON. Dx–
Model Line for this Datasheet
Text Version of Document
link to page 25 link to page 59 link to page 35
Data Sheet AD7293
For RF applications, the use of high Q capacitors functioning as The ADC is used in its single-ended mode. The LSB size varies a filter protects the integrity of the measurement. Connect these with the different supply monitoring registers. AVDD and DACVDD-BI capacitors between the base and the emitter, as close to the are divided by 5, and DACVDD-UNI is divided by 20 to scale within external device as possible. However, large capacitances affect the 0 V to REFADC range. AVSS is divided by 8 and level shifted the accuracy of the temperature measurement; therefore, the to within a −7.5 V to +2.5 V range, where 0x000 equates to recommended maximum capacitor value is 100 pF. In most approximately −7.5 V, and 0xFFF equates to approximately cases, a capacitor is not required; the selection of any capacitor +2.5 V. REFADC = 1.25 V. For RSx+MON (internal monitoring of is dependent on the noise frequency level. the voltage on the RS0+ to RS3+ pins), divide by 50 to scale The AD7293 automatically cancels out the effect of parasitic, them to the 0 V to REFADC range. For BI-VOUTxMON, divide by 8 base, and collector resistance on the temperature reading. This and level shift within a −5 V to +5 V range, where 0x000 cancelation gives a more accurate result, without the need for equates to approximately −5 V, and 0xFFF equates to approx- any user characterization of the parasitic resistance. The AD7293 imately +5 V. The RSx+MON monitor result registers store the 12-bit can compensate for up to 4 kΩ series resistance typically. ADC results for the current sense supply channels (see Figure 42).
AD7293 0V TO +62.5V 0V TO +1.25V RS0+MON 0V TO +62.5V 0V TO +1.25V RS1+MON 2N3904 0V TO +62.5V 0V TO +1.25V RS2+MON NPN Dx+ 10pF 0V TO +62.5V 0V TO +1.25V RS3+MON Dx– –5V TO +5V 0V TO +1.25V
042
BI-VOUT0MON –5V TO +5V 0V TO +1.25V BI-VOUT1MON 12-BIT
13016-
MUX –5V TO +5V 0V TO +1.25V SAR ADC
Figure 40. Measuring Temperature Using a NPN Transistor
BI-VOUT2MON –5V TO +5V 0V TO +1.25V BI-VOUT3MON AD7293 0V TO +6.25V 0V TO +1.25V DACVDD-BI 0V TO 25V 0V TO +1.25V DACVDD-UNI –7.5V TO +2.5V 0V TO +1.25V Dx+ AVSS 10pF 0V TO +6.25V 0V TO +1.25V
044 6-
2N3906 AVDD PNP Dx–
1301 043 Figure 42. Internal Channel Monitoring 13016- Figure 41. Measuring Temperature Using a PNP Transistor
DAC OPERATION Table 15. Temperature Sensor Data Format
The AD7293 contains eight 12-bit DACs, four bipolar DACs,
Temperature TSENSEx Result Registers (Page 0x00,
and four unipolar DACs. These provide digital control with 12 bits
(°C) Register 0x20 to Register 0x22), Bits[D15:D4]
of resolution combined with offset range select registers and a −40 0110 1100 0000 2.5 V internal reference. The DAC core is a 12-bit string DAC. The −25 0111 0011 1000 resistor string structure consists of a string of resistors, each of −10 0111 1011 0000 Value R. The code loaded to the DAC register determines at −0.125 0111 1111 1111 which node on the string the voltage is tapped off to be fed into 0 1000 0000 0000 the output amplifier. When one of the switches connecting the +0.125 1000 0000 0001 string to an amplifier is closed, the voltage is tapped off. This +10 1000 0101 0000 architecture is inherently monotonic and linear. The eight DACs +25 1000 1100 1000 are split into two groups based on their output range. +50 1001 10 01 0000
Bipolar DACs
+75 1010 0101 1000 The bipolar DACs (BI-V +100 1011 0010 0000 OUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3) can be configured through the offset range registers to 0 V to +125 1011 1110 1000 +5 V, −5 V to 0 V, or −4 V to +1 V (see Table 85).
INTERNAL CHANNEL MONITORING
Writing to these register addresses sets the 12-bit DAC output The ADC can internally read the outputs of the four bipolar voltage. There is also a load bit and a copy bit (see Table 27). DACs, AVDD, DACVDD-UNI, DACVDD-BI, AVSS, and the voltage on If the load bit is set to 1, the device waits for LDAC to become the RS0+ to RS3+ pins in the background. A sequencer is active before loading the voltage codes onto the DACs rather than available that allows multiple channels to be converted in a immediately after the write operation. If the copy bit is set to 1 predetermined sequence. when writing to a bipolar DAC register, it sets all bipolar DAC registers to the same value in open-loop mode only. Rev. D | Page 25 of 79 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ADC DAC TEMPERATURE SENSOR CURRENT SENSOR CLOSED-LOOP SPECIFICATIONS GENERAL TIMING CHARACTERISTICS SPI Serial Interface Asynchronous Inputs Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Pseudo Differential Mode CURRENT SENSOR Choosing the External Sense Resistor (RSENSE) TEMPERATURE SENSOR INTERNAL CHANNEL MONITORING DAC OPERATION Bipolar DACs Unipolar DACs DAC Enabling and Clamping Software Clamping: Internal ALERT0 Routing PMOS Drain Switch Control REFERENCE VDRIVE FEATURE OPEN-LOOP MODE CLOSED-LOOP MODE Adjustable Closed-Loop Setpoint Ramp Time Fast Ramp Feature Closed-Loop Sequencing Closed-Loop Integrator Programmable Voltage Limit Closed-Loop Range Upper Voltage Limit DIGITAL INPUT/OUTPUT REGISTERS LOAD DAC (LDAC PIN) Instantaneous DAC Updating (Asynchronous) Deferred DAC Updating (Synchronous) ALERTS AND LIMITS ALERTx Pins Software Alerts Page GPIO0 to GPIO3 Routing to ALERT1 AVDD AND AVSS ALARM MAXIMUM AND MINIMUM PAGES HYSTERESIS REGISTER SETTINGS REGISTERS COMMON TO ALL PAGES No Op Register (Register 0x00) Page Select Pointer Register (Register 0x01) Conversion Command (Register 0x02) Result Register (Register 0x03) DAC Enable Register (Register 0x04) GPIO Register (Register 0x05) Device ID Register (Register 0x0C) Software Reset Register (Register 0x0F) RESULT 0/DAC INPUT (PAGE 0x00) Voltage Input (VINx) Result Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEINT and TSENSEDx) Result Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Result Registers (Register 0x28 to Register 0x2B) DAC Input (UNI-VOUTx and BI-VOUTx) Registers (Register 0x30 to Register 0x37) RESULT 1 (PAGE 0x01) Voltage Supply Monitor Result Registers (Register 0x10 to Register 0x13) Bipolar DAC Internal Monitor Result (BI-VOUT0MON to BI-VOUT3MON) Registers (Register 0x14 to Register 0x17) RSx+MON Result Registers (Register 0x28 to Register 0x2B) CONFIGURATION (PAGE 0x02) Digital Output Enable Register (Register 0x11) Digital Input/Output Function Register (Register 0x12) Digital Functional Polarity Register (Register 0x13) General Register (Register 0x14) VINx Range x Registers (Register 0x15 and Register 0x16) VINx Differential/Single-Ended Enable Register (Register 0x17) VINx Filter Register (Register 0x18) VINx Background Enable Register (Register 0x19) Conversion Delay Register (Register 0x1A) Temperature Sensor (TSENSEx) Background Enable Register (Register 0x1B) Current Sensor (ISENSEx) Background Enable Register (Register 0x1C) Current Sensor (ISENSEx) Gain Register (Register 0x1D) DAC Snooze/SLEEP0 Pin Register (Register 0x1F) DAC Snooze/SLEEP1 Pin Register (Register 0x20) RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23) Integrator Limit and Closed-Loop Control Register (Register 0x28) PA_ON Control Register (Register 0x29) Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D) Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E) Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F) SEQUENCE (PAGE 0x03) Voltage Input (VINx) Sequence Register (Register 0x10) Current Sensor (ISENSEx) and Temperature Sensor (TSENSEx) Sequence Register (Register 0x11) RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence Register (Register 0x12) HIGH LIMIT 0 (PAGE 0x04) VINx High Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) High Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) High Limit Registers (Register 0x28 to Register 0x2B) HIGH LIMIT 1 (PAGE 0x05) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON High Limit Registers (Register 0x14 to Register 0x17) RSx+MON High Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 0 (PAGE 0x06) VINx Low Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Low Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Low Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 1 (PAGE 0x07) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Low Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Low Limit Registers (Register 0x14 to Register 0x17) RSx+MON Low Limit Registers (Register 0x28 to Register 0x2B) HYSTERESIS 0 (PAGE 0x08) VINx Hysteresis Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Hysteresis Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Hysteresis Registers (Register 0x28 to Register 0x2B) HYSTERESIS 1 (PAGE 0x09) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Hysteresis Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Hysteresis Registers (Register 0x14 to Register 0x17) RSx+MON Hysteresis Registers (Register 0x28 to Register 0x2B) MINIMUM 0 (PAGE 0x0A) VINx Minimum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Minimum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Minimum Registers (Register 0x28 to Register 0x2B) MINIMUM 1 (PAGE 0x0B) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Minimum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Minimum Registers (Register 0x14 to Register 0x17) RSx+MON Minimum Registers (Register 0x28 to Register 0x2B) MAXIMUM 0 (PAGE 0x0C) VINx Maximum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Maximum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Maximum Registers (Register 0x28 to Register 0x2B) MAXIMUM 1 (PAGE 0x0D) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Maximum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Maximum Registers (Register 0x14 to Register 0x17) RSx+MON Maximum Registers (Register 0x28 to Register 0x2B) OFFSET 0 (PAGE 0x0E) VINx Offset Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Offset Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Offset Registers (Register 0x28 to Register 0x2B) Unipolar DAC (UNI-VOUTx) Offset Registers (Register 0x30 to Register 0x33) Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) OFFSET 1 (PAGE 0x0F) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Offset Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Offset Registers (Register 0x14 to Register 0x17) RSx+MON Offset Registers (Register 0x28 to Register 0x2B) ALERT (PAGE 0x10) Alert Summary (ALERTSUM) Register (Register 0x10) VINx Alert Register (Register 0x12) Temperature Sensor (TSENSEx) Alert Register (Register 0x14) Current Sensor (ISENSEx) Alert Register (Register 0x15) Supply and BI-VOUTxMON Alert Register (Register 0x18) RSx+MON Alert Register (Register 0x19) INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A) ALERT0 PIN ROUTING (PAGE 0x11) VINx ALERT0 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT0 Register (Register 0x14) Current Sensor (ISENSEx) ALERT0 Register (Register 0x15) Supply and BI-VOUTxMON ALERT0 Register (Register 0x18) RSx+MON ALERT0 Register (Register 0x19) INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A) ALERT1 PIN ROUTING (PAGE 0x12) VINx ALERT1 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT1 Register (Register 0x14) Current Sensor (ISENSEx) ALERT1 Register (Register 0x15) Supply and BI-VOUTxMON ALERT1 Register (Register 0x18) RSx+MON ALERT1 Register (Register 0x19) INTLIMITx and AVSS/AVDD ALERT1 Register (Register 0x1A) SERIAL PORT INTERFACE INTERFACE PROTOCOL MODES OF OPERTION Background Mode (BG) Command Mode Current Sensor and Temperature Sensor Conversions Conversion Timing Current Sense and Temperature Sense Channel Integration Time Conversion and Integration Timing Example 1 Conversion and Integration Timing Example 2 Digital Filtering APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER CONTROL DEPLETION MODE AMPLIFIER BIASING AND PROTECTION LOOP COMPONENT SELECTION OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7293
For RF applications, the use of high Q capacitors functioning as The ADC is used in its single-ended mode. The LSB size varies a filter protects the integrity of the measurement. Connect these with the different supply monitoring registers. AVDD and DACVDD-BI capacitors between the base and the emitter, as close to the are divided by 5, and DACVDD-UNI is divided by 20 to scale within external device as possible. However, large capacitances affect the 0 V to REFADC range. AVSS is divided by 8 and level shifted the accuracy of the temperature measurement; therefore, the to within a −7.5 V to +2.5 V range, where 0x000 equates to recommended maximum capacitor value is 100 pF. In most approximately −7.5 V, and 0xFFF equates to approximately cases, a capacitor is not required; the selection of any capacitor +2.5 V. REFADC = 1.25 V. For RSx+MON (internal monitoring of is dependent on the noise frequency level. the voltage on the RS0+ to RS3+ pins), divide by 50 to scale The AD7293 automatically cancels out the effect of parasitic, them to the 0 V to REFADC range. For BI-VOUTxMON, divide by 8 base, and collector resistance on the temperature reading. This and level shift within a −5 V to +5 V range, where 0x000 cancelation gives a more accurate result, without the need for equates to approximately −5 V, and 0xFFF equates to approx- any user characterization of the parasitic resistance. The AD7293 imately +5 V. The RSx+MON monitor result registers store the 12-bit can compensate for up to 4 kΩ series resistance typically. ADC results for the current sense supply channels (see Figure 42).
AD7293 0V TO +62.5V 0V TO +1.25V RS0+MON 0V TO +62.5V 0V TO +1.25V RS1+MON 2N3904 0V TO +62.5V 0V TO +1.25V RS2+MON NPN Dx+ 10pF 0V TO +62.5V 0V TO +1.25V RS3+MON Dx– –5V TO +5V 0V TO +1.25V
042
BI-VOUT0MON –5V TO +5V 0V TO +1.25V BI-VOUT1MON 12-BIT
13016-
MUX –5V TO +5V 0V TO +1.25V SAR ADC
Figure 40. Measuring Temperature Using a NPN Transistor
BI-VOUT2MON –5V TO +5V 0V TO +1.25V BI-VOUT3MON AD7293 0V TO +6.25V 0V TO +1.25V DACVDD-BI 0V TO 25V 0V TO +1.25V DACVDD-UNI –7.5V TO +2.5V 0V TO +1.25V Dx+ AVSS 10pF 0V TO +6.25V 0V TO +1.25V
044 6-
2N3906 AVDD PNP Dx–
1301 043 Figure 42. Internal Channel Monitoring 13016- Figure 41. Measuring Temperature Using a PNP Transistor
DAC OPERATION Table 15. Temperature Sensor Data Format
The AD7293 contains eight 12-bit DACs, four bipolar DACs,
Temperature TSENSEx Result Registers (Page 0x00,
and four unipolar DACs. These provide digital control with 12 bits
(°C) Register 0x20 to Register 0x22), Bits[D15:D4]
of resolution combined with offset range select registers and a −40 0110 1100 0000 2.5 V internal reference. The DAC core is a 12-bit string DAC. The −25 0111 0011 1000 resistor string structure consists of a string of resistors, each of −10 0111 1011 0000 Value R. The code loaded to the DAC register determines at −0.125 0111 1111 1111 which node on the string the voltage is tapped off to be fed into 0 1000 0000 0000 the output amplifier. When one of the switches connecting the +0.125 1000 0000 0001 string to an amplifier is closed, the voltage is tapped off. This +10 1000 0101 0000 architecture is inherently monotonic and linear. The eight DACs +25 1000 1100 1000 are split into two groups based on their output range. +50 1001 10 01 0000
Bipolar DACs
+75 1010 0101 1000 The bipolar DACs (BI-V +100 1011 0010 0000 OUT0, BI-VOUT1, BI-VOUT2, and BI-VOUT3) can be configured through the offset range registers to 0 V to +125 1011 1110 1000 +5 V, −5 V to 0 V, or −4 V to +1 V (see Table 85).
INTERNAL CHANNEL MONITORING
Writing to these register addresses sets the 12-bit DAC output The ADC can internally read the outputs of the four bipolar voltage. There is also a load bit and a copy bit (see Table 27). DACs, AVDD, DACVDD-UNI, DACVDD-BI, AVSS, and the voltage on If the load bit is set to 1, the device waits for LDAC to become the RS0+ to RS3+ pins in the background. A sequencer is active before loading the voltage codes onto the DACs rather than available that allows multiple channels to be converted in a immediately after the write operation. If the copy bit is set to 1 predetermined sequence. when writing to a bipolar DAC register, it sets all bipolar DAC registers to the same value in open-loop mode only. Rev. D | Page 25 of 79 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ADC DAC TEMPERATURE SENSOR CURRENT SENSOR CLOSED-LOOP SPECIFICATIONS GENERAL TIMING CHARACTERISTICS SPI Serial Interface Asynchronous Inputs Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Pseudo Differential Mode CURRENT SENSOR Choosing the External Sense Resistor (RSENSE) TEMPERATURE SENSOR INTERNAL CHANNEL MONITORING DAC OPERATION Bipolar DACs Unipolar DACs DAC Enabling and Clamping Software Clamping: Internal ALERT0 Routing PMOS Drain Switch Control REFERENCE VDRIVE FEATURE OPEN-LOOP MODE CLOSED-LOOP MODE Adjustable Closed-Loop Setpoint Ramp Time Fast Ramp Feature Closed-Loop Sequencing Closed-Loop Integrator Programmable Voltage Limit Closed-Loop Range Upper Voltage Limit DIGITAL INPUT/OUTPUT REGISTERS LOAD DAC (LDAC PIN) Instantaneous DAC Updating (Asynchronous) Deferred DAC Updating (Synchronous) ALERTS AND LIMITS ALERTx Pins Software Alerts Page GPIO0 to GPIO3 Routing to ALERT1 AVDD AND AVSS ALARM MAXIMUM AND MINIMUM PAGES HYSTERESIS REGISTER SETTINGS REGISTERS COMMON TO ALL PAGES No Op Register (Register 0x00) Page Select Pointer Register (Register 0x01) Conversion Command (Register 0x02) Result Register (Register 0x03) DAC Enable Register (Register 0x04) GPIO Register (Register 0x05) Device ID Register (Register 0x0C) Software Reset Register (Register 0x0F) RESULT 0/DAC INPUT (PAGE 0x00) Voltage Input (VINx) Result Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEINT and TSENSEDx) Result Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Result Registers (Register 0x28 to Register 0x2B) DAC Input (UNI-VOUTx and BI-VOUTx) Registers (Register 0x30 to Register 0x37) RESULT 1 (PAGE 0x01) Voltage Supply Monitor Result Registers (Register 0x10 to Register 0x13) Bipolar DAC Internal Monitor Result (BI-VOUT0MON to BI-VOUT3MON) Registers (Register 0x14 to Register 0x17) RSx+MON Result Registers (Register 0x28 to Register 0x2B) CONFIGURATION (PAGE 0x02) Digital Output Enable Register (Register 0x11) Digital Input/Output Function Register (Register 0x12) Digital Functional Polarity Register (Register 0x13) General Register (Register 0x14) VINx Range x Registers (Register 0x15 and Register 0x16) VINx Differential/Single-Ended Enable Register (Register 0x17) VINx Filter Register (Register 0x18) VINx Background Enable Register (Register 0x19) Conversion Delay Register (Register 0x1A) Temperature Sensor (TSENSEx) Background Enable Register (Register 0x1B) Current Sensor (ISENSEx) Background Enable Register (Register 0x1C) Current Sensor (ISENSEx) Gain Register (Register 0x1D) DAC Snooze/SLEEP0 Pin Register (Register 0x1F) DAC Snooze/SLEEP1 Pin Register (Register 0x20) RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23) Integrator Limit and Closed-Loop Control Register (Register 0x28) PA_ON Control Register (Register 0x29) Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D) Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E) Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F) SEQUENCE (PAGE 0x03) Voltage Input (VINx) Sequence Register (Register 0x10) Current Sensor (ISENSEx) and Temperature Sensor (TSENSEx) Sequence Register (Register 0x11) RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence Register (Register 0x12) HIGH LIMIT 0 (PAGE 0x04) VINx High Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) High Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) High Limit Registers (Register 0x28 to Register 0x2B) HIGH LIMIT 1 (PAGE 0x05) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON High Limit Registers (Register 0x14 to Register 0x17) RSx+MON High Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 0 (PAGE 0x06) VINx Low Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Low Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Low Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 1 (PAGE 0x07) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Low Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Low Limit Registers (Register 0x14 to Register 0x17) RSx+MON Low Limit Registers (Register 0x28 to Register 0x2B) HYSTERESIS 0 (PAGE 0x08) VINx Hysteresis Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Hysteresis Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Hysteresis Registers (Register 0x28 to Register 0x2B) HYSTERESIS 1 (PAGE 0x09) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Hysteresis Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Hysteresis Registers (Register 0x14 to Register 0x17) RSx+MON Hysteresis Registers (Register 0x28 to Register 0x2B) MINIMUM 0 (PAGE 0x0A) VINx Minimum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Minimum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Minimum Registers (Register 0x28 to Register 0x2B) MINIMUM 1 (PAGE 0x0B) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Minimum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Minimum Registers (Register 0x14 to Register 0x17) RSx+MON Minimum Registers (Register 0x28 to Register 0x2B) MAXIMUM 0 (PAGE 0x0C) VINx Maximum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Maximum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Maximum Registers (Register 0x28 to Register 0x2B) MAXIMUM 1 (PAGE 0x0D) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Maximum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Maximum Registers (Register 0x14 to Register 0x17) RSx+MON Maximum Registers (Register 0x28 to Register 0x2B) OFFSET 0 (PAGE 0x0E) VINx Offset Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Offset Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Offset Registers (Register 0x28 to Register 0x2B) Unipolar DAC (UNI-VOUTx) Offset Registers (Register 0x30 to Register 0x33) Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) OFFSET 1 (PAGE 0x0F) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Offset Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Offset Registers (Register 0x14 to Register 0x17) RSx+MON Offset Registers (Register 0x28 to Register 0x2B) ALERT (PAGE 0x10) Alert Summary (ALERTSUM) Register (Register 0x10) VINx Alert Register (Register 0x12) Temperature Sensor (TSENSEx) Alert Register (Register 0x14) Current Sensor (ISENSEx) Alert Register (Register 0x15) Supply and BI-VOUTxMON Alert Register (Register 0x18) RSx+MON Alert Register (Register 0x19) INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A) ALERT0 PIN ROUTING (PAGE 0x11) VINx ALERT0 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT0 Register (Register 0x14) Current Sensor (ISENSEx) ALERT0 Register (Register 0x15) Supply and BI-VOUTxMON ALERT0 Register (Register 0x18) RSx+MON ALERT0 Register (Register 0x19) INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A) ALERT1 PIN ROUTING (PAGE 0x12) VINx ALERT1 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT1 Register (Register 0x14) Current Sensor (ISENSEx) ALERT1 Register (Register 0x15) Supply and BI-VOUTxMON ALERT1 Register (Register 0x18) RSx+MON ALERT1 Register (Register 0x19) INTLIMITx and AVSS/AVDD ALERT1 Register (Register 0x1A) SERIAL PORT INTERFACE INTERFACE PROTOCOL MODES OF OPERTION Background Mode (BG) Command Mode Current Sensor and Temperature Sensor Conversions Conversion Timing Current Sense and Temperature Sense Channel Integration Time Conversion and Integration Timing Example 1 Conversion and Integration Timing Example 2 Digital Filtering APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER CONTROL DEPLETION MODE AMPLIFIER BIASING AND PROTECTION LOOP COMPONENT SELECTION OUTLINE DIMENSIONS ORDERING GUIDE