Datasheet ADAS1000, ADAS1000-1, ADAS1000-2 (Analog Devices) - 8

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ADAS1000/ ADAS1000-1/ ADAS1000-2 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
CLOCK_IO External clock source supplied to CLK_IO; this pin is configured as an input when the device is programmed as a slave Operating Frequency2 8.192 MHz Input Duty Cycle2 20 80 % Output Duty Cycle2 50 % DIGITAL INPUTS Applies to all digital inputs Input Low Voltage, VIL 0.3 × IOVDD V Input High Voltage, VIH 0.7 × IOVDD V Input Current, IIH, IIL −1 +1 μA −20 +20 μA RESET has an internal pull-up Pin Capacitance2 3 pF DIGITAL OUTPUTS Output Low Voltage, VOL 0.4 V ISINK = 1 mA Output High Voltage, VOH IOVDD − 0.4 V ISOURCE = −1 mA Output Rise/Fall Time 4 ns Capacitive load = 15 pF, 20% to 80% DVDD REGULATOR Internal 1.8 V regulator for DVDD Output Voltage 1.75 1.8 1.85 V Available Current1 1 mA Droop < 10 mV; for external device loading purposes Short Circuit Current limit 40 mA ADCVDD REGULATOR Internal 1.8 V regulator for ADCVDD; not recommended as a supply for other circuitry Output Voltage 1.75 1.8 1.85 V Short Circuit Current Limit 40 mA POWER SUPPLY RANGES2 AVDD 3.15 3.3 5.5 V IOVDD 1.65 3.6 V ADCVDD 1.71 1.8 1.89 V If applied by external 1.8 V regulator DVDD 1.71 1.8 1.89 V If applied by external 1.8 V regulator POWER SUPPLY CURRENTS AVDD Standby Current 785 975 μA IOVDD Standby Current 1 60 μA EXTERNALLY SUPPLIED ADCVDD All 5 channels enabled, RLD enabled, pace enabled AND DVDD AVDD Current 3.4 6.25 mA High performance mode 3.1 5.3 mA Low performance mode 4.25 6.3 mA High performance mode, respiration enabled ADCVDD Current 6.2 9 mA High performance mode 4.7 6.5 mA Low performance mode 7 9 mA High performance mode, respiration enabled DVDD Current 2.7 5 mA High performance mode 1.4 3.5 mA Low performance mode 3.4 5.5 mA High performance mode, respiration enabled INTERNALLY SUPPLIED ADCVDD All 5 channels enabled, RLD enabled, pace enabled AND DVDD AVDD Current 12.5 15.3 mA High performance mode 9.4 12.4 mA Low performance mode 14.8 17.3 mA High performance mode, respiration enabled POWER DISSIPATION All 5 channels enabled, RLD enabled, pace enabled Externally Supplied ADCVDD and DVDD3 All 5 Input Channels and RLD 27 mW High performance (low noise) 21 mW Low power mode Internally Supplied ADCVDD All 5 channels enabled, RLD enabled, pace enabled and DVDD All 5 Input Channels and RLD 41 mW High performance (low noise) 31 mW Low power mode Rev. C | Page 8 of 85 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Noise Performance Timing Characteristics Standard Serial Interface Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ADAS1000-1 Only Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Applications Information Overview ECG Inputs—Electrodes/Leads ECG Channel Electrode/Lead Formation and Input Stage Configuration Analog Lead Mode and Calculation Digital Lead Mode and Calculation Electrode Mode: Single-Ended Input Electrode Configuration Electrode Mode: Common Electrode A and Electrode B Configurations Defibrillator Protection ESIS Filtering ECG Path Input Multiplexing Common-Mode Selection and Averaging Wilson Central Terminal (WCT) Right Leg Drive/Reference Drive Calibration DAC Gain Calibration Lead-Off Detection DC Lead-Off Detection DC Lead-Off and High Gains DC Lead-Off Debounce Timer AC Lead-Off Detection ACLO and Common-Mode Configuration ADC Out of Range Shield Driver Respiration (ADAS1000 Model Only) Internal Respiration Capacitors External Respiration Path External Respiration Capacitors Respiration Carrier Frequency Evaluating Respiration Performance Extend Switch On Respiration Paths Pacing Artifact Detection Function (ADAS1000 Only) Choice of Leads Detection Algorithm Overview Pace Edge Threshold Pace Level Threshold Pace Amplitude Threshold Pace Validation Filters Pace Width Filter Biventricular Pacers Pace Detection Measurements Evaluating Pace Detection Performance Pace Width Pace Latency Pace Detection via Secondary Serial Interface (ADAS1000 and ADAS1000-1 Only) Filtering Voltage Reference Gang Mode Operation Master/Slave Synchronizing Devices Calibration Common Mode Right Leg Drive Sequencing Devices into Gang Mode Number of Devices in Gang Mode Interfacing in Gang Mode Serial Interfaces Standard Serial Interface Write Mode Write/Read Data Format Data Frames/Packets Read Mode Serial Clock Rate Data Rate and Skip Mode Data Ready (DRDYB) Detecting Missed Conversion Data SPI Interface Resync CRC Word Clocks Secondary Serial Interface RESETB PDB Function SPI Output Frame Structure (ECG and Status Data) SPI Register Definitions and Memory Map Control Registers Details Examples of Interfacing to the ADAS1000 Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data Example 2: Enable Respiration and Stream Conversion Data Example 3: DC Lead-Off and Stream Conversion Data Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Example 5: Enable Pace Detection and Stream Conversion Data Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Slave Configuration Master Configuration Software Flowchart Power Supply, Grounding, and Decoupling Strategy AVDD ADCVDD and DVDD Supplies Unused Pins/Paths Layout Recommendations Outline Dimensions Ordering Guide