Datasheet ADAS1000-3, ADAS1000-4 (Analog Devices) - 33

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Data Sheet ADAS1000-3/ADAS1000-4 DEFIBRILLATOR PROTECTION ESIS FILTERING
The ADAS1000-3/ADAS1000-4 do not include defibril ation The ADAS1000-3/ADAS1000-4 do not include electrosurgical protection on chip. Any defibril ation protection required by interference suppression (ESIS) protection on chip. Any ESIS the application requires external components. Figure 61 and protection required by the application requires external Figure 62 show examples of external defibril ator protection, components. which is required on each ECG channel, in the RLD path, and
ECG PATH INPUT MULTIPLEXING
in the CM_IN path if using the CE input mode. Note that, in both cases, the total ECG path resistance is assumed to be 5 kΩ. As shown in Figure 63, signal paths for numerous functions are The 22 MΩ resistors shown connected to RLD are optional and provided on each ECG channel (except respiration, which only used to provide a safe termination voltage for an open ECG connects to the ECG1_LA, ECG2_LL, and ECG3_RA pins). electrode; they may be larger in value. Note that, if using these Note that the channel enable switch occurs after the RLD resistors, the dc lead-off feature works best with the highest amplifier connection, thus al owing the RLD to be connected current setting. (redirected into any one of the ECG paths). The CM_IN path is treated the same as the ECG signals.
PATIENT CABLE 4kΩ 500Ω 500Ω ELECTRODE ECG1 AVDD 22M ARGON/NEON Ω1 BULB ADAS1000-3/ RLD SP724 ADAS1000-4 PATIENT 22MΩ1 CABLE 4kΩ 500Ω 500Ω ELECTRODE ECG2 AVDD ARGON/NEON BULB SP724
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1OPTIONAL.
10997- Figure 61. Possible Defibrillation Protection on ECG Paths Using Neon Bulbs
PATIENT CABLE 4.5kΩ 500Ω ELECTRODE ECG1 AVDD 22MΩ1 SP7242 ADAS1000-3/ RLD ADAS1000-4 PATIENT 22MΩ1 CABLE 4.5kΩ 500Ω ELECTRODE ECG2 AVDD SP7242 1OPTIONAL.
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2TWO LITTELFUSE SP724 CHANNELS PER ELECTRODE MAY PROVIDE BEST PROTECTION.
10997- Figure 62. Possible Defibrillation Protection on ECG Paths Using Diode Protection
ACLO CURRENT RESPIRATION DCLO RLD AMP INPUT CURRENT 11.3pF CALDAC INPUT AMPLIFIER ECG PIN + CHANNEL – ENABLE TO FILTERING MUX FOR LEAD CONFIG, ANALOG COMMON ELECTRODE LEAD (RA/LA/LL) + 1.3V VCM_REF VCM – FROM CM AVERAGING TO CM
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ADAS1000 AVERAGING
10997- Figure 63. Typical ECG Channel Input Multiplexing Rev. B | Page 33 of 80 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS NOISE PERFORMANCE TIMING CHARACTERISTICS Standard Serial Interface Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000-4 Only ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION OVERVIEW ECG INPUTS—ELECTRODES/LEADS ECG CHANNEL ELECTRODE/LEAD FORMATION AND INPUT STAGE CONFIGURATION Analog Lead Mode and Calculation Digital Lead Mode and Calculation Electrode Mode: Single-Ended Input Electrode Configuration Electrode Mode: Common Electrode A and Common Electrode B Configurations DEFIBRILLATOR PROTECTION ESIS FILTERING ECG PATH INPUT MULTIPLEXING COMMON-MODE SELECTION AND AVERAGING WILSON CENTRAL TERMINAL (WCT) RIGHT LEG DRIVE/REFERENCE DRIVE CALIBRATION DAC GAIN CALIBRATION LEAD-OFF DETECTION DC Lead-Off Detection DC Lead-Off and High Gains AC Lead-Off Detection ADC Out of Range SHIELD DRIVER RESPIRATION (ADAS1000-4 MODEL ONLY) Internal Respiration Capacitors External Respiration Path External Respiration Capacitors Respiration Carrier Frequency EVALUATING RESPIRATION PERFORMANCE PACING ARTIFACT DETECTION FUNCTION (ADAS1000-4 ONLY) Choice of Leads Detection Algorithm Overview Pace Edge Threshold Pace Level Threshold Pace Amplitude Threshold Pace Validation Filters Pace Width Filter BIVENTRICULAR PACERS PACE DETECTION MEASUREMENTS EVALUATING PACE DETECTION PERFORMANCE PACE WIDTH PACE LATENCY PACE DETECTION VIA SECONDARY SERIAL INTERFACE FILTERING VOLTAGE REFERENCE GANG MODE OPERATION Master/Slave Synchronizing Devices Calibration Common Mode Right Leg Drive Sequencing Devices into Gang Mode INTERFACING IN GANG MODE SERIAL INTERFACES STANDARD SERIAL INTERFACE Write Mode Write/Read Data Format Data Frames/Packets Read Mode Serial Clock Rate Data Rate and Skip Mode Data Ready (DRDY) Detecting Missed Conversion Data CRC Word Clocks SECONDARY SERIAL INTERFACE RESET PD FUNCTION SPI OUTPUT FRAME STRUCTURE (ECG AND STATUS DATA) SPI REGISTER DEFINITIONS AND MEMORY MAP CONTROL REGISTERS DETAILS INTERFACE EXAMPLES Example 1: Initialize the Device for ECG Capture and Start Streaming Data Example 2: Enable Respiration and Stream Conversion Data (Applies to ADAS1000-4 Only) Example 3: DC Lead-Off and Stream Conversion Data Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Example 5: Enable Pace Detection and Stream Conversion Data (Applies to ADAS1000-4 Only) Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Slave Configuration (ADAS1000-3) Master Configuration (ADAS1000) SOFTWARE FLOWCHART POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY AVDD ADCVDD AND DVDD SUPPLIES UNUSED PINS/PATHS LAYOUT RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE