Datasheet ADRV9008-2 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Integrated Dual RF Transmitter and Observation Receiver |
| Pages / Page | 95 / 4 — ADRV9008-2. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Symbol. Min. … |
| File Format / Size | PDF / 2.5 Mb |
| Document Language | English |
ADRV9008-2. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Symbol. Min. Typ. Max. Unit. Test Conditions/Comments
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ADRV9008-2 Data Sheet SPECIFICATIONS
Electrical characteristics at VDDA1P31 = 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V, TJ = full operating temperature range. Local oscillator frequency (fLO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics section for input/output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows: transmitter = 50 MHz/100 MHz bandwidth (inphase quadrature (IQ) rate = 122.88 MHz), observation receiver = 100 MHz bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device configuration for all other frequency ranges is as follows: transmitter = 200 MHz/450 MHz bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTERS Center Frequency
75 6000 MHz Transmitter (Tx) 450 MHz Synthesis Bandwidth (BW) Transmitter Large Signal 200 MHz Bandwidth (3G/4G) Transmitter Large Signal 75 MHz Low intermediate frequency (IF) Bandwidth (MC GSM) mode Peak-to-Peak Gain 1.0 dB 450 MHz bandwidth, compensated Deviation by programmable finite impulse response (FIR) filter Gain Slope ±0.1 dB Any 20 MHz bandwidth span, compensated by programmable FIR filter Deviation from Linear 1 Degrees 450 MHz bandwidth Phase Transmitter Attenuation 0 32 dB Signal-to-noise ratio (SNR) maintained Power Control Range for attenuation between 0 dB and 20 dB Transmitter Attenuation 0.05 dB Power Control Resolution
Transmitter Attenuation INL 0.1 dB For any 4 dB step Integral Nonlinearity Transmitter Attenuation DNL ±0.04 dB Monotonic Differential Nonlinearity Transmitter Attenuation See Figure 4 Serial Peripheral Interface 2 (SPI 2) Timing Time from CS Going tSCH 19.5 24 ns High to Change in Transmitter Attenuation Time Between tACH 6.5 8.1 ns A large change in attenuation can Consecutive be broken up into a series of smaller Microattenuation attenuation changes Steps Time Required to Reach tDCH 800 ns Time required to complete the Final Attenuation change in attenuation from start Value attenuation to final attenuation value Maximum Attenuation −1.0 +0.5 dB Overshoot During Transition Rev. 0 | Page 4 of 95 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Terminology Theory of Operation Transmitter Observation Receiver Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-2W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Observation Receiver Path Interface Impedance Matching Network Example Outline Dimensions Ordering Guide
ADRV9008-2 Data Sheet SPECIFICATIONS
Electrical characteristics at VDDA1P31 = 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V, TJ = full operating temperature range. Local oscillator frequency (fLO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics section for input/output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows: transmitter = 50 MHz/100 MHz bandwidth (inphase quadrature (IQ) rate = 122.88 MHz), observation receiver = 100 MHz bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device configuration for all other frequency ranges is as follows: transmitter = 200 MHz/450 MHz bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
TRANSMITTERS Center Frequency
75 6000 MHz Transmitter (Tx) 450 MHz Synthesis Bandwidth (BW) Transmitter Large Signal 200 MHz Bandwidth (3G/4G) Transmitter Large Signal 75 MHz Low intermediate frequency (IF) Bandwidth (MC GSM) mode Peak-to-Peak Gain 1.0 dB 450 MHz bandwidth, compensated Deviation by programmable finite impulse response (FIR) filter Gain Slope ±0.1 dB Any 20 MHz bandwidth span, compensated by programmable FIR filter Deviation from Linear 1 Degrees 450 MHz bandwidth Phase Transmitter Attenuation 0 32 dB Signal-to-noise ratio (SNR) maintained Power Control Range for attenuation between 0 dB and 20 dB Transmitter Attenuation 0.05 dB Power Control Resolution
Transmitter Attenuation INL 0.1 dB For any 4 dB step Integral Nonlinearity Transmitter Attenuation DNL ±0.04 dB Monotonic Differential Nonlinearity Transmitter Attenuation See Figure 4 Serial Peripheral Interface 2 (SPI 2) Timing Time from CS Going tSCH 19.5 24 ns High to Change in Transmitter Attenuation Time Between tACH 6.5 8.1 ns A large change in attenuation can Consecutive be broken up into a series of smaller Microattenuation attenuation changes Steps Time Required to Reach tDCH 800 ns Time required to complete the Final Attenuation change in attenuation from start Value attenuation to final attenuation value Maximum Attenuation −1.0 +0.5 dB Overshoot During Transition Rev. 0 | Page 4 of 95 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Terminology Theory of Operation Transmitter Observation Receiver Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-2W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Observation Receiver Path Interface Impedance Matching Network Example Outline Dimensions Ordering Guide
