Datasheet AD9375 (Analog Devices) - 56

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AD9375 Data Sheet THEORY OF OPERATION
The AD9375 is a highly integrated RF transceiver that can be
RECEIVER (Rx)
configured for a wide range of applications. The device integrates The AD9375 contains dual receiver channels. Each Rx channel all the RF, mixed-signal, and digital blocks necessary to provide is a direct conversion system that contains a programmable transmit and receive functions in a single device. Programmability attenuator stage, fol owed by matched I and Q mixers that allows the two receiver channels and two transmitter channels downconvert received signals to baseband for digitization. to be used in TDD and FDD systems for 3G and 4G cellular standards. To achieve gain control, a programmed gain index map is implemented. This gain map distributes attenuation among the The observation receiver channel has two inputs for use in various Rx blocks for optimal performance at each power level. monitoring the transmitter outputs. This channel has a wide In addition, support is available for both automatic and manual channel bandwidth that receives the entire transmit band and gain control modes. feeds it back to the digital section for error correction purposes. In addition, three sniffer receiver inputs can monitor different The receiver includes Σ-Δ ADCs and adjustable sample rates radio frequency bands (one at a time). These channels share the that produce data streams from the received signals. The signals baseband ADC and digital processing with the two ORx inputs. can be conditioned further by a series of decimation filters and a ful y programmable 72-tap FIR filter with additional decimation The AD9375 contains four high speed serial interface links for settings. The sample rate of each digital filter block is adjustable the transmit chain and four high speed serial interface links by changing the decimation factors to produce the desired shared by the Rx, ORx, and SnRx channels (JESD204B, output data rate. Subclass 1 compliant), providing a low pin count and reliable data interface to a field-programmable gate array (FPGA) or
OBSERVATION RECEIVER (ORx)
other custom integrated baseband solutions. The ORx operates in a similar manner to the main receivers. The AD9375 also provides self calibration for dc offset and Each input is differential and uses a dedicated mixer. The ORx quadrature error correction to maintain a high performance inputs share a baseband ADC and baseband section; therefore, level under varying temperatures and input signal conditions. only one can be active at any time. The mixed signal and digital The device includes test modes that allow system designers to section is identical in design and operation to the main receiver debug designs during prototyping and optimize radio channels. This channel can monitor the Tx channels and configurations. implement error correction functions. It can also be used as a general-purpose receiver.
TRANSMITTER (Tx) SNIFFER RECEIVER (SnRx)
The AD9375 employs a direct conversion transmitter architecture consisting of two identical and independently The sniffer receiver provides three differential inputs that can controlled channels that provide all the digital processing, monitor different frequency bands. Each input has a low noise mixed-signal, and RF blocks necessary to implement a direct amplifier (LNA) that is multiplexed to feed a single mixer. The conversion system. Both channels share a common frequency output of this mixer stage is multiplexed with the ORx receiver synthesizer. mixers to feed the same baseband section. The SnRx bandwidth is limited to 20 MHz. This receiver can also be used as a general- The digital data from the JESD204B lanes pass through a fully purpose receiver if the bandwidth and RF performance are programmable 96-tap FIR filter with optional interpolation. acceptable for a given application. The sniffer channel is also The FIR output is sent to a series of conversion filters that limited to operation from 300 MHz to 4000 MHz. Performance provide additional filtering and data rate interpolation prior to cannot be guaranteed for LO settings above 4000 MHz. reaching the DAC. Each DAC has an adjustable sample rate and is linear up to full scale. These receiver inputs also provide an LNA bypass mode that removes the gain of the LNA when large signals are present. Once converted to baseband analog signals, the in-phase (I) and Note that no requirements for the LNA bypass mode are included quadrature (Q) signals are filtered to remove sampling artifacts, in Table 1; performance specifications are only relative to the and then the signals are fed to the upconversion mixers. At the scenario in which the LNA is enabled. mixer stage, the I and Q signals are recombined and modulated onto the carrier frequency for transmission to the output stage.
CLOCK INPUT
Each transmit chain provides a wide attenuation adjustment The AD9375 requires a differential clock connected to the range with fine granularity to help designers optimize SNR. DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the clock input must be between 10 MHz and 320 MHz, and it must have very low phase noise because this signal generates the RF local oscillator and internal sampling clocks. Rev. 0 | Page 56 of 61 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 700 MHz Band 2.6 GHz Band 3.5 GHz Band 5.5 GHz Band Theory of Operation Transmitter (Tx) Receiver (Rx) Observation Receiver (ORx) Sniffer Receiver (SnRx) Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) GPIO_x AND GPIO_3P3_x Pins Auxiliary Converters Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs (AUXDAC_x) JESD204B Data Interface Power Supply Sequence Digital Predistortion (DPD) JTAG Boundary Scan Outline Dimensions Ordering Guide