Datasheet ADN8835 (Analog Devices) - 21

Data Sheet ADN8835 Inductor Selection Capacitor Selection
The inductor selection determines the inductor current ripple and The output capacitor selection determines the output voltage loop dynamic response. Larger inductance results in smal er ripple, transient response, as well as the loop dynamic response current ripple and slower transient response because smaller of the PWM amplifier output. Use the fol owing equation to inductance results in the opposite performance. To optimize the select the capacitor: performance, the trade-off must be made between transient V × ( SW _OUT VIN –V ) response speed, efficiency, and component size. Calculate the SW _OUT C = V × 8× L× ( f 2 ) × V ∆ inductor value with the fol owing equation: IN SW OUT V ×( Note that the voltage caused by the product of current ripple, SW _OUT VIN –V ) SW OUT L = _ ΔI V × × ∆ L, and the capacitor equivalent series resistance (ESR) also IN fSW IL add up to the total output voltage ripple. Selecting a capacitor where: with low ESR can increase overal regulation and efficiency VSW_OUT is the PWM amplifier output. performance. fSW is the switching frequency (2 MHz by default). ∆I
Table 8. Recommended Output Capacitors
L is the inductor current ripple.
Footprint Vendor Value Device No. (mm)
A 1 µH inductor is typical y recommended to al ow reasonable Murata 10 µF ± ZRB18AD71A106KE01L 1.6 × 0.8 output capacitor selection while maintaining a low inductor 10%, 10 V current ripple. If lower inductance is required, a minimum Murata 10 µF ± GRM188D71A106MA73 1.6 × 0.8 inductor value of 0.68 µH is suggested to ensure that the current 20%, 10 V ripple is set to a value between 30% and 40% of the maximum Taiyo 10 µF ± LMK107BC6106MA-T 1.6 × 0.8 Yuden 20%, 10 V load current. Except for the inductor value, the equivalent dc resistance (DCR)
INPUT CAPACITOR SELECTION
inherent in the metal conductor is also a critical factor for On the PVIN pin, the amplifiers require an input capacitor inductor selection. The DCR accounts for most of the power loss to decouple the noise and to provide the transient current to on the inductor by DCR × I 2 OUT . Using an inductor with high maintain a stable input and output voltage. A 10 µF ceramic DCR degrades the overal efficiency significantly. In addition, capacitor rated at 10 V is the minimum recommended value. there is a conduct voltage drop across the inductor because of Increasing the capacitance reduces the switching ripple that the DCR. When the PWM amplifier is sinking current in cooling couples into the power supply but increases the capacitor size. mode, this voltage drives the minimum voltage of the amplifier Because the current at the input terminal of the PWM amplifier higher than 0.06 × VPVIN by at least tenth of mil ivolts. Similarly, the is discontinuous, a capacitor with low effective series inductance maximum PWM amplifier output voltage is lower than 0.93 × (ESL) is preferred to reduce voltage spikes. VPVIN. In most applications, a decoupling capacitor is used in parallel This voltage drop is proportional to the value of the DCR, and with the input capacitor. The decoupling capacitor is usual y a reduces the output voltage range at the TEC. 100 nF ceramic capacitor with very low ESR and ESL, which When selecting an inductor, ensure that the saturation current provides better noise rejection at high frequency bands. rating is higher than the maximum current peak to prevent sat-
POWER DISSIPATION
uration. In general, ceramic multilayer inductors are suitable for low This section provides guidelines to calculate the power current applications due to small size and low DCR. When the dissipation of the ADN8835. Approximate the total power noise level is critical, use a shielded ferrite inductor to reduce the dissipation in the device by electromagnetic interference (EMI). PLOSS = PPWM + PLINEAR
Table 7. Recommended Inductors
where:
Vendor Value Device No. Footprint (mm)
PPWM is the power dissipation in the PWM regulator. Coilcraft 1.0 μH ± XFL4020-102MEB 4.3 × 4.3 P 20% LOSS is the total power dissipation in the ADN8835. P Murata 1.0 μH ± DFE252012P-1R0M 2.5 × 2.0 LINEAR is the power dissipation in the linear regulator. 20%
PWM Regulator Power Dissipation
The PWM power stage is configured as a buck regulator and its dominant power dissipation (PPWM) includes power switch Rev. B | Page 21 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE