Datasheet ADN8834 (Analog Devices) - 13

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Data Sheet ADN8834 THEORY OF OPERATION
The ADN8834 is a single chip TEC controller that sets and The ADN8834 drives its internal MOSFET transistors to provide stabilizes a TEC temperature. A voltage applied to the input of the TEC current. To provide good power efficiency and zero the ADN8834 corresponds to the temperature setpoint of the target crossing quality, only one side of the H-bridge uses a PWM object attached to the TEC. The ADN8834 controls an internal driver. Only one inductor and one capacitor are required to filter FET H-bridge whereby the direction of the current fed through out the switching frequency. The other side of the H-bridge uses a the TEC can be either positive (for cooling mode), to pump linear output without requiring any additional circuitry. This pro- heat away from the object attached to the TEC, or negative (for prietary configuration al ows the ADN8834 to provide efficiency of heating mode), to pump heat into the object attached to the TEC. >90%. For most applications, a 1 µH inductor, a 10 μF capacitor, Temperature is measured with a thermal sensor attached to the and a switching frequency of 2 MHz maintain less than 1% of the target object and the sensed temperature (voltage) is fed back to worst-case output voltage ripple across a TEC. the ADN8834 to complete a closed thermal control loop of the The maximum voltage across the TEC and the current flowing TEC. For the best overall stability, couple the thermal sensor through the TEC are set by using the VLIM/SD and ILIM pins. close to the TEC. In most laser diode modules, a TEC and a The maximum cooling and heating currents can be set indepen- NTC thermistor are already mounted in the same package to dently to allow asymmetric heating and cooling limits. For regulate the laser diode temperature. additional details, see the Maximum TEC Voltage Limit section The TEC is differential y driven in an H-bridge configuration. and the Maximum TEC Current Limit section.
TEC CURRENT ENABLE/ TEC SYNC VOLTAGE SHUTDOWN CVDD V 0.1µF IN RBP 2.7V TO 5.5V EN/SY ITEC VTEC VDD VLIM/SD TEC PVIN R R C V1 V2 IN VOLTAGE 10µF LIMIT TEC ILIM CURRENT RC1 R LIMITS C2 LDR C TEC L_OUT ADN8834 0.1µF + VREF PGNDL CVREF – 0.1µF R RA AGND SFB TEMP L = 1µH SET IN2P IN1P SW CSW_OUT IN1N OUT1 IN2N OUT2 PGNDS 10µF R R X B RFB R C R I NTC I P RTH R C D D CF THERMISTER
019 12954- Figure 26. Typical Application Circuit with Analog PID Compensation in a Temperature Control Loop Rev. B | Page 13 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide