Datasheet ADN8834 (Analog Devices) - 27
| Manufacturer | Analog Devices |
| Description | Ultra compact 1.5 A Thermoelectric Cooler (TEC) Controller |
| Pages / Page | 27 / 27 — Data Sheet. ADN8834. OUTLINE DIMENSIONS. 2.58 2.54 SQ. BOTTOM VIEW. 2.50. … |
| Revision | B |
| File Format / Size | PDF / 978 Kb |
| Document Language | English |
Data Sheet. ADN8834. OUTLINE DIMENSIONS. 2.58 2.54 SQ. BOTTOM VIEW. 2.50. (BALL SIDE UP). BALL A1. IDENTIFIER. 2.00. REF. 0.50. BSC. TOP VIEW
Model Line for this Datasheet
Text Version of Document
link to page 27 link to page 27
Data Sheet ADN8834 OUTLINE DIMENSIONS 2.58 2.54 SQ BOTTOM VIEW 2.50 (BALL SIDE UP) 5 4 3 2 1 A BALL A1 IDENTIFIER 2.00 B REF C 0.50 BSC D E TOP VIEW (BALL SIDE DOWN) 0.390 0.660 0.360 0.600 END VIEW 0.330 0.540 COPLANARITY 0.05 SEATING 0.270 0.360 PLANE 0.240 0.320 0.210 A 0.280 2013- -003121 07- G K P 06-
Figure 44. 25-Ball Wafer Level Chip Scale Package [WLCSP] (CB-25-7) Dimensions shown in millimeters
4.10 0.30 4.00 SQ 0.25 3.90 PIN 1 0.18 INDICATOR PIN 1 19 24 INDICATOR 18 1 0.50 BSC 2.70 EXPOSED 2.60 SQ PAD 2.50 13 6 0.50 12 7 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF A 2013- -004273 03- G K P COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. 12-
Figure 45. 24-Lead Lead-frame Chip Scale Package [LFCSP_WQ] (CP-24-15) Dimensions shown in millimeters
ORDERING GUIDE Package Model1 Temperature Range2 Package Description Option
ADN8834ACBZ-R7 −40°C to +125°C 25-Ball Wafer Level Chip Scale Package [WLCSP] CB-25-7 ADN8834CB-EVALZ 25-Ball WLCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit ADN8834ACPZ-R2 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-15 ADN8834ACPZ-R7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-15 ADN8834CP-EVALZ 24-Lead LFCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit ADN8834MB-EVALZ Mother Evaluation Board of the ADN8834 for PID tuning 1 Z = RoHS Compliant Part. 2 Operating junction temperature range. The ambient operating temperature range is −40°C to +85°C.
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12954-0-9/18(B)
Rev. B | Page 27 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide
Data Sheet ADN8834 OUTLINE DIMENSIONS 2.58 2.54 SQ BOTTOM VIEW 2.50 (BALL SIDE UP) 5 4 3 2 1 A BALL A1 IDENTIFIER 2.00 B REF C 0.50 BSC D E TOP VIEW (BALL SIDE DOWN) 0.390 0.660 0.360 0.600 END VIEW 0.330 0.540 COPLANARITY 0.05 SEATING 0.270 0.360 PLANE 0.240 0.320 0.210 A 0.280 2013- -003121 07- G K P 06-
Figure 44. 25-Ball Wafer Level Chip Scale Package [WLCSP] (CB-25-7) Dimensions shown in millimeters
4.10 0.30 4.00 SQ 0.25 3.90 PIN 1 0.18 INDICATOR PIN 1 19 24 INDICATOR 18 1 0.50 BSC 2.70 EXPOSED 2.60 SQ PAD 2.50 13 6 0.50 12 7 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF A 2013- -004273 03- G K P COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. 12-
Figure 45. 24-Lead Lead-frame Chip Scale Package [LFCSP_WQ] (CP-24-15) Dimensions shown in millimeters
ORDERING GUIDE Package Model1 Temperature Range2 Package Description Option
ADN8834ACBZ-R7 −40°C to +125°C 25-Ball Wafer Level Chip Scale Package [WLCSP] CB-25-7 ADN8834CB-EVALZ 25-Ball WLCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit ADN8834ACPZ-R2 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-15 ADN8834ACPZ-R7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-15 ADN8834CP-EVALZ 24-Lead LFCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit ADN8834MB-EVALZ Mother Evaluation Board of the ADN8834 for PID tuning 1 Z = RoHS Compliant Part. 2 Operating junction temperature range. The ambient operating temperature range is −40°C to +85°C.
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12954-0-9/18(B)
Rev. B | Page 27 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide
