Datasheet ADCMP608 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| Pages / Page | 10 / 8 — ADCMP608. Data Sheet. 500mV OVERDRIVE. CROSSOVER BIAS POINT. INPUT … |
| Revision | B |
| File Format / Size | PDF / 237 Kb |
| Document Language | English |
ADCMP608. Data Sheet. 500mV OVERDRIVE. CROSSOVER BIAS POINT. INPUT VOLTAGE. 10mV OVERDRIVE. N ± VOS. DISPERSION. Q OUTPUT
Model Line for this Datasheet
Text Version of Document
link to page 7
ADCMP608 Data Sheet 500mV OVERDRIVE CROSSOVER BIAS POINT
Rail-to-rail inputs of this type, in both op amps and comparators,
INPUT VOLTAGE
have a dual front-end design. Certain devices are active near the
10mV OVERDRIVE
VCC rail and others are active near the VEE rail. At some
V
predetermined point in the common-mode range, a crossover
N ± VOS
occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset 0 voltages and currents.
DISPERSION
-01 9
Q OUTPUT
76 06 The ADCMP608 slightly elaborates on this scheme. Crossover Figure 10. Propagation Delay—Overdrive Dispersion points can be found at approximately 0.8 V and 1.6 V.
MINIMUM INPUT SLEW RATE REQUIREMENT INPUT VOLTAGE
With the rated load capacitance and normal good PC board
1V/ns
design practice, as discussed in the Optimizing Performance
VN ± VOS
section, these comparators should be stable at any input slew
10V/ns
rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation may be encountered. These oscillations
DISPERSION
1 01 are due to the high gain bandwidth of the comparator in 9-
Q OUTPUT
76 06 combination with feedback through parasitics in the package Figure 11. Propagation Delay—Slew Rate Dispersion and PC board. In many applications, chattering is not harmful. Rev. B | Page 8 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
ADCMP608 Data Sheet 500mV OVERDRIVE CROSSOVER BIAS POINT
Rail-to-rail inputs of this type, in both op amps and comparators,
INPUT VOLTAGE
have a dual front-end design. Certain devices are active near the
10mV OVERDRIVE
VCC rail and others are active near the VEE rail. At some
V
predetermined point in the common-mode range, a crossover
N ± VOS
occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset 0 voltages and currents.
DISPERSION
-01 9
Q OUTPUT
76 06 The ADCMP608 slightly elaborates on this scheme. Crossover Figure 10. Propagation Delay—Overdrive Dispersion points can be found at approximately 0.8 V and 1.6 V.
MINIMUM INPUT SLEW RATE REQUIREMENT INPUT VOLTAGE
With the rated load capacitance and normal good PC board
1V/ns
design practice, as discussed in the Optimizing Performance
VN ± VOS
section, these comparators should be stable at any input slew
10V/ns
rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation may be encountered. These oscillations
DISPERSION
1 01 are due to the high gain bandwidth of the comparator in 9-
Q OUTPUT
76 06 combination with feedback through parasitics in the package Figure 11. Propagation Delay—Slew Rate Dispersion and PC board. In many applications, chattering is not harmful. Rev. B | Page 8 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
