Datasheet HMC674LC3C, HMC674LP3E (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 9.3 GHz Latched Comparator with RSPECL Output Stage |
| Pages / Page | 14 / 10 — HMC674LC3C/HMC674LP3E. Data Sheet. THEORY OF OPERATION. POWER SEQUENCING |
| Revision | K |
| File Format / Size | PDF / 331 Kb |
| Document Language | English |
HMC674LC3C/HMC674LP3E. Data Sheet. THEORY OF OPERATION. POWER SEQUENCING
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HMC674LC3C/HMC674LP3E Data Sheet THEORY OF OPERATION
The HMC674LC3C/HMC674LP3E are latched comparators
POWER SEQUENCING
with a 9.3 GHz equivalent input bandwidth. These devices are As long as the input signal is not near the −2 V extreme, either comprised of three blocks: an input amplifier, a latch, and an VCC or VEE can be powered on first. However, if the input voltage is output buffer. The latching circuit is level sensitive and consists more negative than −1.8 V, use the following power-up sequence: of a single, high speed latch. The HMC674LC3C/HMC674LP3E comparators support 10 Gbps operation. The input signal 1. VEE minimum pulse width is 60 ps. 2. VCCI and VCCO (if VCCO = VCCI) 3. VCCO (if different than ground) The HMC674LC3C/HMC674LP3E operate in either track (transparent) mode, where the output fol ows the logical value Note that the power-down sequence is the reverse of this of the input, or latch (hold) mode, where the output value is held sequence. to the logical value of the comparison result of the input just It is recommended to power up the HMC674LC3C or the prior to (LE − LE) going high. Select track mode operation by HMC674LP3E before applying the input signal and to remove the either setting (LE − LE) low or by floating the LE and LE inputs. input signal prior to powering either down. These recommendations Select latch mode by setting (LE − LE) high. The input impedance are important if any of the inputs are more negative than −1.8 V. of the LE and LE inputs is 8 kΩ; however, these inputs can be terminated with 50 Ω external resistors, if desired. When the clock inputs are dc-coupled, they operate at an input common-mode voltage of 2 V. In this case, any termination resistors ideally return to 2 V. If the clock inputs are ac-coupled to the HMC674LC3C/HMC674LP3E, return the input termination resistors to ground. Rev. K | Page 10 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LATCH ENABLE (LE/) SPECIFICATIONS DC OUTPUT SPECIFICATIONS AC SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TIMING DESCRIPTIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
The HMC674LC3C/HMC674LP3E are latched comparators
POWER SEQUENCING
with a 9.3 GHz equivalent input bandwidth. These devices are As long as the input signal is not near the −2 V extreme, either comprised of three blocks: an input amplifier, a latch, and an VCC or VEE can be powered on first. However, if the input voltage is output buffer. The latching circuit is level sensitive and consists more negative than −1.8 V, use the following power-up sequence: of a single, high speed latch. The HMC674LC3C/HMC674LP3E comparators support 10 Gbps operation. The input signal 1. VEE minimum pulse width is 60 ps. 2. VCCI and VCCO (if VCCO = VCCI) 3. VCCO (if different than ground) The HMC674LC3C/HMC674LP3E operate in either track (transparent) mode, where the output fol ows the logical value Note that the power-down sequence is the reverse of this of the input, or latch (hold) mode, where the output value is held sequence. to the logical value of the comparison result of the input just It is recommended to power up the HMC674LC3C or the prior to (LE − LE) going high. Select track mode operation by HMC674LP3E before applying the input signal and to remove the either setting (LE − LE) low or by floating the LE and LE inputs. input signal prior to powering either down. These recommendations Select latch mode by setting (LE − LE) high. The input impedance are important if any of the inputs are more negative than −1.8 V. of the LE and LE inputs is 8 kΩ; however, these inputs can be terminated with 50 Ω external resistors, if desired. When the clock inputs are dc-coupled, they operate at an input common-mode voltage of 2 V. In this case, any termination resistors ideally return to 2 V. If the clock inputs are ac-coupled to the HMC674LC3C/HMC674LP3E, return the input termination resistors to ground. Rev. K | Page 10 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LATCH ENABLE (LE/) SPECIFICATIONS DC OUTPUT SPECIFICATIONS AC SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TIMING DESCRIPTIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
