Datasheet ADM7155 (Analog Devices) - 20

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ADM7155 Data Sheet 155 Thermal Characterization Parameter (ΨJB) 145
When board temperature is known, use the thermal
135 125
characterization parameter, ΨJB, to estimate the junction
(°C) 115
temperature rise (see Figure 62 and Figure 63). Maximum
URE
junction temperature (T
AT 102
J) is calculated from the board
R E 95
temperature (T
P
B) and power dissipation (PD) using the following
M E 85
formula:
N T 75 IO
TJ = TB + (PD × ΨJB) (5)
65 CT 55
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP
JUN 6400mm2 45 500mm2
package and 17.9°C/W for the 8-lead SOIC package.
35 25mm2 T 160 25 J MAX 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
58 0
140 TOTAL POWER DISSIPATION (W)
325- 12
)
Figure 59. Junction Temperature vs. Total Power Dissipation for
(°C 120 E
the 8-Lead SOIC, TA = 25°C
R TU 100 160 A R E 150 P 80 M ) 140 TE 60 (°C ON E 130 TI R C T U N 40 B = 25°C 120 T AT JU B = 50°C R T E 110 20 B = 65°C P TB = 85°C M E 100 TJ MAX 0 N T
1
90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0
06
IO TOTAL POWER DISSIPATION (W)
325-
80
12
NCT JU 6400mm2
Figure 62. Junction Temperature vs. Total Power Dissipation for
70 500mm2
the 8-Lead LFCSP
60 25mm2 T 160 50 J MAX
9
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
05
140 TOTAL POWER DISSIPATION (W)
325- 12 Figure 60. Junction Temperature vs. Total Power Dissipation for
(°C) 120
the 8-Lead SOIC, TA = 50°C
URE 100 155 AT R E P 80 145 M E ) 135 N T 60 (°C IO E R CT T U 125 40 B = 25°C T AT JUN B = 50°C R T E 115 20 B = 65°C P TB = 85°C M E 105 TJ MAX 0 N T 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
62 0
IO 95 TOTAL POWER DISSIPATION (W)
325- 12
NCT 85 JU 6400mm2
Figure 63. Junction Temperature vs. Total Power Dissipation for
500mm2
the 8-Lead SOIC
75 25mm2 T PSRR PERFORMANCE 65 J MAX
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
06 The ADM7155 is available in four models that optimize power
TOTAL POWER DISSIPATION (W)
325- 12 dissipation and PSRR performance as a function of input and Figure 61. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, T output voltage. See Table 9 and Table 10 for selection guides. A = 85°C Rev. C | Page 20 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PSRR PERFORMANCE PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE