Datasheet ADM7150 (Analog Devices) - 20
| Manufacturer | Analog Devices |
| Description | 800 mA Ultralow Noise, High PSRR, RF Linear Regulator |
| Pages / Page | 24 / 20 — ADM7150. Data Sheet. 155. 145. 135. °C). 125. 115. URE. 102. RAT E. M E. … |
| File Format / Size | PDF / 831 Kb |
| Document Language | English |
ADM7150. Data Sheet. 155. 145. 135. °C). 125. 115. URE. 102. RAT E. M E. N T. 105. RAT. JUNCT. 6400mm2. 500mm2. 25mm2. TJ MAX
Model Line for this Datasheet
- ADM7150ACPZ-1.8-R2 ADM7150ACPZ-1.8-R7 ADM7150ACPZ-3.3-R2 ADM7150ACPZ-3.3-R7 ADM7150ACPZ-4.5-R2 ADM7150ACPZ-4.5-R7 ADM7150ACPZ-4.8-R2 ADM7150ACPZ-4.8-R7 ADM7150ACPZ-5.0-R2 ADM7150ACPZ-5.0-R7 ADM7150ARDZ-1.8 ADM7150ARDZ-2.8 ADM7150ARDZ-3.0 ADM7150ARDZ-3.0-R7 ADM7150ARDZ-3.3 ADM7150ARDZ-3.3-R7 ADM7150ARDZ-5.0 ADM7150ARDZ-5.0-R7
Text Version of Document
link to page 20 link to page 20
ADM7150 Data Sheet
Figure 63 to Figure 68 show junction temperature calculations for
155
different ambient temperatures, power dissipation, and areas of
145
PCB copper.
135 °C) 125 155 ( 115 145 URE 102 135 RAT E 95 P °C) 125 ( M E 85 115 URE N T 75 105 IO RAT 65 E 95 P 55 M JUNCT 6400mm2 E 85 45 500mm2 N T 75 25mm2 IO 35 65 TJ MAX 25 55 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
066
JUNCT 6400mm2 45 500mm2 TOTAL POWER DISSIPATION (W)
1043- 1
25mm2 35
Figure 66. Junction Temperature vs. Total Power Dissipation for
TJ MAX 25
the 8-Lead SOIC, TA = 25°C 063
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 160 TOTAL POWER DISSIPATION (W)
1043- 1 Figure 63. Junction Temperature vs. Total Power Dissipation for
150
the 8-Lead LFCSP, TA = 25°C
140 °C) 160 ( 130 150 URE 120 RAT 140 E 110 P °C) ( M 130 E 100 URE 120 N T 90 IO RAT E 110 80 P M JUNCT 6400mm2 E 100 70 500mm2 N T 90 60 25mm2 IO TJ MAX 80 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
067
JUNCT 6400mm2 70 500mm2 TOTAL POWER DISSIPATION (W)
1043- 1
60 25mm2
Figure 67. Junction Temperature vs. Total Power Dissipation for
TJ MAX 50
the 8-Lead SOIC, TA = 50°C 064
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 155 TOTAL POWER DISSIPATION (W)
11043- Figure 64. Junction Temperature vs. Total Power Dissipation for
145
the 8-Lead LFCSP, TA = 50°C
°C) 135 155 ( URE 125 145 RAT E 115 P °C) 135 ( M E 105 URE 125 N T IO 95 RAT E 115 P 85 M JUNCT 6400mm2 E 105 500mm2 N T 75 25mm2 IO 95 TJ MAX 65 85 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
068
JUNCT 6400mm2 500mm2 TOTAL POWER DISSIPATION (W)
1043- 1
75 25mm2
Figure 68. Junction Temperature vs. Total Power Dissipation for
TJ MAX 65
the 8-Lead SOIC, TA = 85°C
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
065
TOTAL POWER DISSIPATION (W)
1043- 1 Figure 65. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, TA = 85°C Rev. 0 | Page 20 of 24 Document Outline Features Applications General Description Typical Application Circuit Table of Contents Revision History Specifications Input and Output Capacitor Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties Enable (EN) and Undervoltage Lockout (UVLO) Start-Up Time REF, BYP, and, VREG pins Current-Limit and Thermal Overload Protection Thermal Considerations Thermal Characterization Parameter (ΨJB) Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide
ADM7150 Data Sheet
Figure 63 to Figure 68 show junction temperature calculations for
155
different ambient temperatures, power dissipation, and areas of
145
PCB copper.
135 °C) 125 155 ( 115 145 URE 102 135 RAT E 95 P °C) 125 ( M E 85 115 URE N T 75 105 IO RAT 65 E 95 P 55 M JUNCT 6400mm2 E 85 45 500mm2 N T 75 25mm2 IO 35 65 TJ MAX 25 55 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
066
JUNCT 6400mm2 45 500mm2 TOTAL POWER DISSIPATION (W)
1043- 1
25mm2 35
Figure 66. Junction Temperature vs. Total Power Dissipation for
TJ MAX 25
the 8-Lead SOIC, TA = 25°C 063
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 160 TOTAL POWER DISSIPATION (W)
1043- 1 Figure 63. Junction Temperature vs. Total Power Dissipation for
150
the 8-Lead LFCSP, TA = 25°C
140 °C) 160 ( 130 150 URE 120 RAT 140 E 110 P °C) ( M 130 E 100 URE 120 N T 90 IO RAT E 110 80 P M JUNCT 6400mm2 E 100 70 500mm2 N T 90 60 25mm2 IO TJ MAX 80 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
067
JUNCT 6400mm2 70 500mm2 TOTAL POWER DISSIPATION (W)
1043- 1
60 25mm2
Figure 67. Junction Temperature vs. Total Power Dissipation for
TJ MAX 50
the 8-Lead SOIC, TA = 50°C 064
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 155 TOTAL POWER DISSIPATION (W)
11043- Figure 64. Junction Temperature vs. Total Power Dissipation for
145
the 8-Lead LFCSP, TA = 50°C
°C) 135 155 ( URE 125 145 RAT E 115 P °C) 135 ( M E 105 URE 125 N T IO 95 RAT E 115 P 85 M JUNCT 6400mm2 E 105 500mm2 N T 75 25mm2 IO 95 TJ MAX 65 85 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
068
JUNCT 6400mm2 500mm2 TOTAL POWER DISSIPATION (W)
1043- 1
75 25mm2
Figure 68. Junction Temperature vs. Total Power Dissipation for
TJ MAX 65
the 8-Lead SOIC, TA = 85°C
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
065
TOTAL POWER DISSIPATION (W)
1043- 1 Figure 65. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, TA = 85°C Rev. 0 | Page 20 of 24 Document Outline Features Applications General Description Typical Application Circuit Table of Contents Revision History Specifications Input and Output Capacitor Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties Enable (EN) and Undervoltage Lockout (UVLO) Start-Up Time REF, BYP, and, VREG pins Current-Limit and Thermal Overload Protection Thermal Considerations Thermal Characterization Parameter (ΨJB) Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide
