Datasheet ADP170, ADP171 (Analog Devices) - 12

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ADP170/ADP171 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Input Bypass Capacitor Output Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the The ADP170/ADP171 are designed for operation with small, circuit sensitivity to the printed circuit board (PCB) layout, space-saving ceramic capacitors but will function with most especially when long input traces or high source impedance commonly used capacitors as long as care is taken with regard are encountered. If greater than 1 μF of output capacitance is to the effective series resistance (ESR) value. The ESR of the required, the input capacitor should be increased to match it. output capacitor affects the stability of the LDO control loop.
Input and Output Capacitor Properties
A minimum of 1 μF capacitance with an ESR of 1 Ω or less is Any good quality ceramic capacitor can be used with the recommended to ensure stability of the ADP170/ADP171. The ADP170/ADP171, as long as it meets the minimum capacitance transient response to changes in load current is also affected by and maximum ESR requirements. Ceramic capacitors are manu- output capacitance. Using a larger value of output capacitance factured with a variety of dielectrics, each with different behavior improves the transient response of the ADP170/ADP171 to over temperature and applied voltage. Capacitors must have a large changes in load current. Figure 27 and Figure 28 show the dielectric adequate to ensure the minimum capacitance over the transient responses for output capacitance values of 1 μF and necessary temperature range and dc bias conditions. A X5R or X7R 4.7 μF, respectively. dielectric with a voltage rating of 6.3 V or 10 V is recommended.
ILOAD
The Y5V and Z5U dielectrics are not recommended, due to their
1mA TO 300mA LOAD STEP,
poor temperature and dc bias characteristics.
2.5A/µs 1
Figure 29 depicts the capacitance vs. bias voltage characteristics of a 0402, 1 μF, 10 V X5R capacitor. The variance of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating will exhibit less capacitance variance over bias voltage. The
2
temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of
VOUT
package or voltage rating.
VOUT = 1.8V
5
C
12
IN = COUT = 1µF 1.2
6- 71 07
CH1 200mA Ω CH2 50.0mV BW M200ns A CH1 112mA T 500.000ns 1.0
Figure 27. Output Transient Response, COUT = 1 μF
) F 0.8 µ ( ILOAD NCE 1mA TO 300mA LOAD STEP, A 0.6 T 2.5A/µs 1 ACI 0.4 CAP 0.2
5 02 6-
2
71
0
07
V 0 2 4 6 8 10 OUT BIAS VOLTAGE (V) V
Figure 29. Capacitance vs. Bias Voltage Characteristics 6
OUT = 1.8V
12
CIN = COUT = 4.7µF
6- 71 Use Equation 1 to determine the worst-case capacitance 07
CH1 200mA Ω CH2 50.0mV BW M200ns A CH1 108mA
accounting for capacitor variation over temperature,
T 500.000ns
component tolerance, and voltage. Figure 28. Output Transient Response, COUT = 4.7 μF CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. Rev. C | Page 12 of 20 Document Outline Features Applications Typical Application Circuits General Description Table of Contents Revision History Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Undervoltage Lockout Enable Feature Current Limit and Thermal Overload Protection Thermal Considerations Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide