Datasheet AD8251 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 10 MHz, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier |
| Pages / Page | 24 / 5 — AD8251. Parameter. Conditions. Min. Typ. Max. Unit. TIMING DIAGRAM. … |
| Revision | B |
| File Format / Size | PDF / 646 Kb |
| Document Language | English |
AD8251. Parameter. Conditions. Min. Typ. Max. Unit. TIMING DIAGRAM. tWR-HIGH. tWR-LOW. tSU. tHD. A0, A1
Model Line for this Datasheet
Text Version of Document
link to page 17
AD8251 Parameter Conditions Min Typ Max Unit
POWER SUPPLY Operating Range ±5 ±15 V Quiescent Current, +IS 4.1 4.5 mA Quiescent Current, −IS 3.7 4.5 mA Over Temperature T = −40°C to +85°C 4.5 mA TEMPERATURE RANGE Specified Performance −40 +85 °C 1 Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM tWR-HIGH tWR-LOW WR tSU tHD A0, A1
03 -0 87 62 0 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Rev. B | Page 5 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
AD8251 Parameter Conditions Min Typ Max Unit
POWER SUPPLY Operating Range ±5 ±15 V Quiescent Current, +IS 4.1 4.5 mA Quiescent Current, −IS 3.7 4.5 mA Over Temperature T = −40°C to +85°C 4.5 mA TEMPERATURE RANGE Specified Performance −40 +85 °C 1 Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM tWR-HIGH tWR-LOW WR tSU tHD A0, A1
03 -0 87 62 0 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Rev. B | Page 5 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
